VHDL for FPGA Design/4-Bit Adder

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all use ieee.std_logic_arith.all;

Entity Adder4 Is port ( a,b:in integer Range -8 to 7; sum:out integer Range -16 to 15 ); end Adder4;

Architecture Adder4arch of Adder4 Is Begin sum<=a+b;

end Adder4arch;

Simulation Waveform


VHDL-kieli FPGA-suunnittelussa/4-bittinen summain