VHDL for FPGA Design

Combinational Logic

 * 1) /Decoder/
 * 2) /Multiplexer/
 * 3) /Priority Encoder/
 * 4) /4-Bit Adder/
 * 5) /4-Bit Multiplier/
 * 6) /4-Bit ALU/

Sequential Logic

 * 1) /D Flip Flop/
 * 2) /T Flip Flop/
 * 3) /JK Flip Flop/
 * 4) /4-Bit Binary Counter with Parallel Load/
 * 5) /4-Bit BCD Counter with Clock Enable/
 * 6) /4-Bit Shift Register/
 * 7) /4-Bit Johnson Counter with Reset/

State-Machine

 * 1) /State-Machine Design Example Asynchronous Counter/
 * 2) /State-Machine Design Example Serial Parity Generator/

Design Exercises

 * 1) /Example Application Serial Adder/
 * 2) /Example Application Using PicoBlaze/
 * 3) /Complete synthesisable VHDL code for Signed 32 bit Radix-16 multiplier/