User:Yamoksh Verma/sandbox

Structural Description of VHDL The circuit can be descibed using a structural model that specifiers what gates are used and how they are implemented. The following example illustrates it.

architecture structural of BUZZER is  --Declarations component AND2 is   port (in1, in2, :in std_logic;             Out2: out std_logic); end component;

We initialise signal as follows

signal var1, var2 : std_logic text