User:Doruletz72/ONBA/Instructions Set

=INTRODUCTION= Instructions are basic actions of a processor. They are designed to work with the processor registers. Therefore, any instruction that addresses memory locations having at least one register as a parameter. Even if the MOVE instruction when both parameters are memory locations, even in this case the transfer is not actually made directly between the two memory locations, but by successive execution of two instructions MOVE "classical" one, where one parameter is a register.

What is an instruction?
Difficult to answer this question. Instructions can substitute assignment or arithmetic operators, conditional statements or loops, can manipulate memory locations, can invoke system routines, can interrupt or continue the execution of a program. No matter what programming environment is a program written, in the end, it will be transformed by the compiler / assembler in a binary package that represents a collection of instructions to be executed by processor.

A question arises: is the optimal result code? Or it could be improved. For applications developed by large companies, with the participation of a large number of programmers, it could be. But in OnbC compiler/OnbA assembler case, result code is not the best solution, but it is safe. This the main reason to use directly OnbA instead of OnbC.

Format
Any instruction has a mnemonic (a name), followed by operand size and one, two or a set of operands. Some instructions have no operands.


 * MNEMONIC[.SIZE] 
 * MNEMONIC[.SIZE] , 
 * MNEMONIC[.SIZE] /, 
 * MNEMONIC[.SIZE] , /
 * MNEMONIC

For some instructions, size can be: byte (.b), word (.w) or long (.l).

The effective address  can be represented in one of the address modes: Dn, An, (An), (An)+, -(An), (d16, An), (d8, An, Xi), (d16, PC), (d8, PC, Xi), Abs.W, Abs.L, #data, CCR/SR. See the Address Modess chapter. Examples:

Codification
Each instruction is coded on two bytes (word), which means that the code segment is aligned to word size. Some of the operands can be encoded within this word, and the rest in the words immediately following the instruction. If you intend to disassemble the code record of a PRC file, read the first word, identify the instruction and then, interpret the words that follow, depending on the type of instruction that you just identified it. After decoding all the words belonging to the first instruction, the process can continue in the same way to decode the entire code record. Let's get back to the first instruction word. Usually, first four bits of this word contains the binary IDentifier of the instruction. The remaining bits can be codification of the size of the operands, or of the number of the registers used as operands, or of the type of the address mode used for the operands.

Let's consider the instruction ADD - add the source operand to the destination operand, using binary addition and store the result in the destination:
 * Source + Destination -> Destination
 * Synopsis:
 * ADD , Dn
 * ADD Dn, 


 * Operands size: .b, .w, .l
 * Adress Modes:
 * if  is the source: Dn, An*, (An), (An)+, -(An), (d16, An), (d8, An, Xi), (d16, PC), (d8, PC, Xi), Abs.W, Abs.L, #data
 * if  is the destination: (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L
 * An*: size is word or long only.

Normally, this information is enough to use the ADD instruction in the program. But in case you want to disassemble binary PRC data, you will need additional information:
 * Format: 1101,3:Reg,3:OpMode,6:3Mode3Reg (16 bits, first word of the instruction)

Where:
 * 1101 - 4 bits; signature of ADD instruction
 * 3:Reg - 3 bits; the number of Dn register operand (binary codified)
 * 3:OpMode - 3 bits; this field specifies:
 * 1st bit encodes operation order:
 * 0xx  + Dn -> Dn
 * 1xx Dn +  -> <ea>
 * 2nd and 3rd bits encode the operand size:
 * x00 - byte x01 - word x10 - long x11 - not used
 * 6:3Mode3Reg - 6 bits; this codifies address modes of the <ea>; 3Mode field specifies the code of address mode; 3Reg can specifies the number of the register used

As suspected, if the situation requires, first word of instruction may be followed by additional words for the operands values not included in the first word of the instruction.

Additional information is available at http://www.freescale.com/files/archives/doc/ref_manual/M68000PRM.pdf.

=CATEGORIES= Depending on the operating, instructions can be classified as follows: In the followings:
 * Data Movement, Logical, Integer Arithmetic, Bit Manipulation, Shift and Rotation, BCD Arithmetic, Program Control, System Control, CCR and SR.


 * Instruction* - instruction is not implemented by OnbA, but was included in case you want to disassemble a binary file.

Data Movement
A-Z Index │ Categories │ TOP
 * EXG* - exchanges content of two registers
 * LEA - loads effective address
 * LINK - allocates a stack frame
 * MOVE - moves data/address between two registers/memory locations
 * MOVEA - moves address between two registers/memory locations
 * MOVEM - moves contents of multiple registers
 * MOVEP* - moves peripheral data
 * MOVEQ - moves quick with registers
 * PEA - pushes effective address on the stack
 * UNLK - removes a stack frame

 EXG  - EXchanGe registers


 * Exchanges the contents of any two registers.
 * Synopsis:
 * EXG Rx, Ry


 * Operands size: .l
 * Rx -> Ry, Ry -> Rx
 * Address Modes: only Dn and An.
 * Flags(CCR): unaffected.
 * Comments: the values from address registers are always treated as signed values.
 * Format: 1110,3:Rx,1,5:OpMode,3:Ry (16 bits, first word of the instruction)
 * Rx - specifies a data or an address register. If it's an exchange between a data register and an address register, this field defines the data register.
 * Rx - specifies a data or an address register. If it's an exchange between a data register and an address register, this field defines the address register.
 * OpMode:
 * 01000 Exg. between data registers
 * 01001 Exg. between address registers
 * 10001 Exg. between data and address registers

A-Z Index │ Data Movement │ Categories
 * OnbA use: not implemented.

LEA - Load effective address


 * Places the specified address into the destination address register.
 * Synopsis:
 * LEA <ea>, An


 * Operands size: .l
 * Address -> An
 * Address Modes: <ea> can be (An), (An)+, -(An), (d16, An), (d8, An, Xi), (d16, PC), (d8, PC, Xi), Abs.W, Abs.L
 * Flags(CCR): unaffected.
 * Comments: all 32 bits of An register are affected by this instruction.
 * Format: 0100,3:Reg,111,6:3Mode3Reg (16 bits, first word of the instruction)
 * Reg - one of the 8 address registers
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Data Movement │ Categories
 * OnbA use: You should not specify a size.

LINK - Link a frame stack


 * Save an An register content on the stack, then creates a local frame stack referred by this An register. To allocate space on the stack for local data area, a negative value should be used for the second operand.
 * Synopsis:
 * LINK An, #data


 * Operands size: .w
 * SP - 4 -> SP, An -> SP
 * SP -> An
 * SP - #data -> SP
 * Address Modes: An for first parameter and #data for second parameter.
 * Flags(CCR): unaffected.
 * Comments: LINK and UNLK can be used to maintain a linked list of local data and parameter areas on the stack for nested subroutine calls. This is your main instruction to build procedures/routines/functions. Never use A7 register (SP). However if you do this save the value of A7 to a variable, not directly on the stack.
 * Examples:
 * Format: 0100111001010,3:Reg (16 bits, first word of the instruction) + 16 bits offset
 * Reg - indicates the number of address register used.
 * offset - 0 or a negative value which enable to move stack pointer (allocate memory on the stack).

A-Z Index │ Data Movement │ Categories
 * OnbA use:
 * You should not specify a size.
 * directives proc ... local ... beginproc are replaced by OnbA with LINK a6, #-  always.

MOVE - Move data


 * Moves (copies) source to the destination. After the execution, both source and destination contain same data.
 * Synopsis:
 * MOVE <ea>, <ea>


 * Operands size: .b, .w, .l
 * Source -> Destination ; Destination = Source
 * Address Modes:
 * if <ea> is the source: Dn, An*, (An), (An)+, -(An), (d16, An), (d8, An, Xi), (d16, PC), (d8, PC, Xi), Abs.W, Abs.L, #data
 * if <ea> is the destination: Dn, (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L
 * An*: size is word or long only.


 * Flags(CCR):
 * X - not affected
 * N - 1 if result is negative, 0 otherwise
 * Z - 1 if result is zero, 0 otherwise
 * V - 0
 * C - 0


 * Comments: Is the most used instruction, being the equivalent of assignment operator =. The size of the operation may be specified as byte, word or long. When you move to an address register, the value is interpreted as signed. When you move byte or word to a register the upper of the register remains unchanged. See the Address Modes chapter examples.
 * Examples:
 * Format: 00,2:Size,6:3Mode3Reg(Dst),6:3Mode3Reg(Src) (16 bits, first word of the instruction)
 * Size
 * 01 byte 10 word 11 long
 * 3Mode3Reg(Dst), 6:3Mode3Reg(Src) - codifies address modes of the <ea>; see the table above.

A-Z Index │ Data Movement │ Categories
 * OnbA use: - if you don't specify a size, .w is used by default.

MOVEA - Move address


 * Moves (copies) source to the destination address register. After the execution, both source and destination contain same data.
 * Synopsis:
 * MOVE <ea>, An


 * Operands size: .w, .l
 * Source -> An ; An = Source
 * Address Modes: <ea> can be Dn, An*, (An), (An)+, -(An), (d16, An), (d8, An, Xi), (d16, PC), (d8, PC, Xi), Abs.W, Abs.L, #data
 * An*: size is word or long only.


 * Flags(CCR): not affected
 * Comments: Word sized operands are sign extended to the 32 bits before the operation is done.
 * Examples:
 * Format: 00,2:Size,3:Reg,001,6:3Mode3Reg (16 bits, first word of the instruction)
 * Reg - one of the 8 address registers
 * Size
 * 01 byte 10 word 11 long
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Data Movement │ Categories
 * OnbA use: - if you don't specify a size, .w is used by default.

MOVEM - Move multiple registers


 * Moves (copies) source to the destination. After the execution, both source and destination contain same data.
 * Synopsis:
 * MOVEM register_list, <ea>
 * MOVEM <ea>, register_list


 * Operands size: .b, .w, .l
 * Source -> Destination ; Destination = Source
 * Address Modes:
 * if <ea> is the destination (registers to memory): (An), -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L
 * if <ea> is the source (memory to registers): (An), (An)+, (d16, An), (d8, An, Xi), (d16, PC), (d8, PC, Xi), Abs.W, Abs.L
 * An*: size is word or long only.


 * Flags(CCR): not affected.
 * Comments: moves the contents of selected registers to or from consecutive memory locations starting with the location specified by the effective address <ea>. A register is selected if the bit in the mask field corresponding to that register is set. The instruction size determines whether 16 or 32 bits of each register are transferred. In the case of a word transfer to either address or data registers, each word is sign-extended to 32 bits, and the resulting long word is loaded into the associated register. Selecting the addressing mode also selects the mode of operation of the MOVEM instruction, and only the control modes, the predecrement mode, and the postincrement mode are valid. If the effective address is specified by one of the control modes, the registers are transferred starting at the specified address, and the address is incremented by the operand length (2 or 4) following each transfer. The order of the registers is from D0 to D7, then from A0 to A7. If the effective address is specified by the predecrement mode, only a register-to-memory operation is allowed. The registers are stored starting at the specified address minus the operand length (2 or 4), and the address is decremented by the operand length following each transfer. The order of storing is from A7 to A0, then from D7 to D0. When the instruction has completed, the decremented address register contains the address of the last operand stored.
 * Examples:
 * Format: 01001,1:dr,001,1:Size,6:3Mode3Reg (16 bits, first word of the instruction) and word with mask registers list (bits 15 .. 0 | D0, .. D7, A0, .. A7 for predecrement mode or A7, .. A0, D7, .., D0 for postincrement mode).
 * dr - specifies the move direction
 * 0 from regs to <ea> 1 from <ea> to regs
 * Size - data size
 * 0 - 16 bits, 1 - 32 bits
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Data Movement │ Categories
 * OnbA use: - if you don't specify a size, .w is used by default.

MOVEP - Move peripheral


 * Moves (copies) source to the destination. After the execution, both source and destination contain same data.
 * Synopsis:
 * MOVEP Dx, (d,Ay)
 * MOVEP (d,Ay), Dx


 * Operands size: .w, .l
 * Source -> Destination ; Destination = Source
 * Address Modes: Dn for registers, (d16, An) for memory location.
 * Flags(CCR): not affected.
 * Comments: moves data between a data register and alternate bytes within the address space starting at the location specified and incrementing by two. The high-order byte of the data register is transferred first, and the low-order byte is transferred last. The memory address is specified in the address register indirect plus 16-bit displacement addressing mode.
 * Format: 0000,3:Dx,3:OpMode,001,3:Ay (16 bits, first word of the instruction)
 * Dx - specifies the number of the data register
 * OpMode
 * 100 16 bits move, memory to register
 * 101 32 bits move, memory to register
 * 110 16 bits move, register to memory
 * 111 32 bits move, register to memory
 * Ay - specifies the number of the address register

A-Z Index │ Data Movement │ Categories
 * OnbA use: - not implemented.

MOVEQ - Move signed 8-bits data quick


 * Moves (copies) source signed 8-bits data to a data register destination.
 * Synopsis:
 * MOVEQ #data, Dn


 * Operands size: .l
 * immediate data -> Dn
 * Address Modes: #data for source, Dn for destination.
 * Flags(CCR):
 * X - not affected
 * N - 1 if result is negative, 0 otherwise
 * Z - 1 if result is zero, 0 otherwise
 * V - 0
 * C - 0


 * Comments: the specified data is sign extended 32-bits, before is moved to the register.
 * Examples:
 * Format: 0111,3:Reg,0,8:Data (16 bits, first word of the instruction)
 * Reg - is one of the 8 data registers.
 * Data - immediate data (signed)

A-Z Index │ Data Movement │ Categories
 * OnbA use: - You should not specify a size.

PEA - Push effective address


 * Computes the effective address of the operand and pushes it onto the stack.
 * Synopsis:
 * PEA <ea>


 * Operands size: .l
 * SP - 4 -> SP, <ea> -> SP
 * Address Modes: <ea> can be (An), (d16, An), (d8, An, Xi), (d16, PC), (d8, PC, Xi), Abs.W, Abs.L
 * Flags(CCR): not affected
 * Comments: The effective address is a long address. It is used when you want to pass address/pointers to a procedure.
 * Examples:
 * Format: 0100100001,6:3Mode3Reg (16 bits, first word of the instruction)
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Data Movement │ Categories
 * OnbA use: - You should not specify a size.

UNLK - Unlink a stack frame


 * Unlink the stack frame referred by an address register.
 * Synopsis:
 * UNLK An


 * Operands size: .l
 * An -> SP
 * SP -> An, SP + 4 -> SP
 * Address Modes: An
 * Flags(CCR): not affected
 * Comments: Load the stack pointer from the specified address register. Then load the address register with the long word pulled from the top of the stack (pushed by LINK instruction). This instruction does the inverse process of the LINK instruction.
 * Format: 0100111001011,3:Reg (16 bits, first word of the instruction)
 * one of the 8 address registers (previously used by LINK)

A-Z Index │ Data Movement │ Categories
 * OnbA use: - Use along with LINK instruction.

Logical
A-Z Index │ Categories │ TOP
 * AND, ANDI - logical AND / immediate
 * EOR, EORI - exclusive logical OR / immediate
 * NOT - logical NOT (1 complement)
 * OR, ORI - logical OR / immediate

AND - logical AND


 * Perform a bit-wise AND operation with the source operand and the destination operand and stores the result in the destination operand.
 * Synopsis:
 * AND <ea>, Dn
 * AND Dn, <ea>


 * Operands size: .b, .w, .l
 * Source & Destination -> Destination
 * Address Modes:
 * if <ea> is the source: Dn, (An), (An)+, -(An), (d16, An), (d8, An, Xi), (d16, PC), (d8, PC, Xi), Abs.W, Abs.L, #data
 * if <ea> is the destination: (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L


 * Flags(CCR):
 * X - not affected
 * N - 1 if MSBi(result) == 1, 0 otherwise
 * Z - 1 if result is zero, 0 otherwise
 * V - 0
 * C - 0


 * Comments: the contents of an address register may not be used as an operand.
 * Examples:
 * Format: 1100,3:Reg,3:OpMode,6:3Mode3Reg (16 bits, first word of the instruction)
 * Reg - the number of Dn register operand (binary codified)
 * OpMode:
 * 1st bit encodes operation order:
 * 0xx <ea> & Dn -> Dn
 * 1xx Dn & <ea> -> <ea>
 * 2nd and 3rd bits encode the operand size:
 * x00 - byte x01 - word x10 - long x11 - not used
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Logical │ Categories
 * OnbA use: - if you don't specify a size, .w is used by default.

ANDI - logical AND immediate


 * Perform a bit-wise AND operation with the immediate data and the destination operand and stores the result in the destination operand.
 * Synopsis:
 * ANDI #data, <ea>


 * Operands size: .b, .w, .l
 * Immediate Data & Destination -> Destination
 * Address Modes: <ea> can be addressed Dn, (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L
 * Flags(CCR):
 * X - not affected
 * N - 1 if MSBi(result) == 1, 0 otherwise
 * Z - 1 if result is zero, 0 otherwise
 * V - 0
 * C - 0


 * Comments: the size of immediate data matches the operation size.
 * Examples:
 * Format: 00000010,2:Size,6:3Mode3Reg (16 bits, first word of the instruction)
 * Size - specifies how to deal with the words following the instruction (the immediate data)
 * 00 - byte operation (the lower byte of the next word)
 * 01 - word operation (the entire next word)
 * 10 - long operation (the next two words)
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Logical │ Categories
 * OnbA use: - if you don't specify a size, .w is used by default.

EOR - logical exclusive OR


 * Perform a bit-wise exclusive OR operation with the source operand data register and the destination operand and stores the result in the destination operand.
 * Synopsis:
 * EOR Dn, <ea>


 * Operands size: .b, .w, .l
 * Dn ^ Destination -> Destination
 * Address Modes: <ea> can be Dn, (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L
 * Flags(CCR):
 * X - not affected
 * N - = MSBi(result)
 * Z - 1 if result is zero, 0 otherwise
 * V - 0
 * C - 0


 * Comments: two successive EOR operations between same values restore the initial contents of the destination.
 * Examples:
 * Format: 1011,3:Reg,3:OpMode,6:3Mode3Reg (16 bits, first word of the instruction)
 * Reg - the number of Dn register operand (binary codified)
 * OpMode:
 * 100 byte 101 word 110 long
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Logical │ Categories
 * OnbA use: - if you don't specify a size, .w is used by default. Dn mode for <ea> not supported.

EORI - exclusive OR immediate


 * Perform a bit-wise exclusive OR operation with the source immediate data and the destination operand and stores the result in the destination operand.
 * Synopsis:
 * EOR #data, <ea>


 * Operands size: .b, .w, .l
 * Immediate Data ^ Destination -> Destination
 * Address Modes: <ea> can be Dn, (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L
 * Flags(CCR):
 * X - not affected
 * N - = MSBi(result)
 * Z - 1 if result is zero, 0 otherwise
 * V - 0
 * C - 0


 * Comments: same as EOR instruction but operation is performed with immediate data instead of a data register.
 * Examples:
 * Format: 00001010,2:Size,6:3Mode3Reg (16 bits, first word of the instruction) + additional words for immediate data.
 * Size - the number of Dn register operand (binary codified)
 * 00 byte 01 word 10 long
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Logical │ Categories
 * OnbA use: - if you don't specify a size, .w is used by default.

NOT - logical NOT


 * Logical NOT complement (1-complement).
 * Synopsis:
 * NOT <ea>


 * Operands size: .b, .w, .l
 * Destination -> ~Destination
 * Address Modes: <ea> can be Dn, (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L
 * Flags(CCR):
 * X - not affected
 * N - 1 if result < 0, 0 otherwise
 * Z - 1 if result == 0, 0 otherwise
 * V - 0
 * C - 0


 * Comments: All bits of the specified operand are inverted and the result is placed back in the operand. Good to invert the status of bit-variables (flags).
 * Examples:
 * Format: 01000110,2:Size,6:3Mode3Reg (16 bits, first word of the instruction) + additional words for immediate data.
 * Size - the number of Dn register operand (binary codified)
 * 00 byte 01 word 10 long
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Logical │ Categories
 * OnbA use: - if you don't specify a size, .w is used by default.

OR - logical OR


 * Perform a bit-wise OR operation with the source operand and the destination operand and stores the result in the destination operand.
 * Synopsis:
 * OR <ea>, Dn
 * OR Dn, <ea>


 * Operands size: .b, .w, .l
 * Source | Destination -> Destination
 * Address Modes:
 * if <ea> is the source: Dn, (An), (An)+, -(An), (d16, An), (d8, An, Xi), (d16, PC), (d8, PC, Xi), Abs.W, Abs.L, #data
 * if <ea> is the destination: (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L


 * Flags(CCR):
 * X - not affected
 * N - 1 if MSBi(result) == 1, 0 otherwise
 * Z - 1 if result is zero, 0 otherwise
 * V - 0
 * C - 0


 * Comments: the contents of an address register may not be used as an operand.
 * Examples:
 * Format: 1000,3:Reg,3:OpMode,6:3Mode3Reg (16 bits, first word of the instruction)
 * Reg - the number of Dn register operand (binary codified)
 * OpMode:
 * 1st bit encodes operation order:
 * 0xx <ea> & Dn -> Dn
 * 1xx Dn & <ea> -> <ea>
 * 2nd and 3rd bits encode the operand size:
 * x00 - byte x01 - word x10 - long x11 - not used
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Logical │ Categories
 * OnbA use: - if you don't specify a size, .w is used by default.

ORI - logical OR immediate


 * Perform a bit-wise OR operation with the immediate data and the destination operand and stores the result in the destination operand.
 * Synopsis:
 * OR #data, <ea>


 * Operands size: .b, .w, .l
 * Immediate Data | Destination -> Destination
 * Address Modes: <ea> can be addressed Dn, (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L
 * Flags(CCR):
 * X - not affected
 * N - 1 if MSBi(result) == 1, 0 otherwise
 * Z - 1 if result is zero, 0 otherwise
 * V - 0
 * C - 0


 * Comments: the size of immediate data matches the operation size.
 * Examples:
 * Format: 00000000,2:Size,6:3Mode3Reg (16 bits, first word of the instruction)
 * Size - specifies how to deal with the words following the instruction (the immediate data)
 * 00 - byte operation (the lower byte of the next word)
 * 01 - word operation (the entire next word)
 * 10 - long operation (the next two words)
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Logical │ Categories
 * OnbA use: - if you don't specify a size, .w is used by default.

Integer Arithmetic
A-Z Index │ Categories │ TOP
 * ADD, ADDA, ADDI, ADDQ, ADDX - adds value / address / immediate / quick / with extend
 * SUB, SUBA, SUBI, SUBQ, SUBX - subtracts value / address / immediate / quick / with extend
 * MULS, MULU - multiplies signed / unsigned
 * DIVS, DIVU - divides signed / unsigned
 * CMP, CMP2*, CMPA*, CMPI, CMPM* - compares value / with 2 bounds / address / immediate / memory
 * NEG, NEGX - negates value / with extend (2 complement)
 * CLR - clears operand
 * EXT - extends sign and size

 ADD  - Adds an integer


 * Adds the source operand to the destination operand.
 * Synopsis:
 * ADD <ea>, Dn
 * ADD Dn, <ea>


 * Operands size: .b, .w, .l
 * Source + Destination -> Destination
 * Address Modes:
 * if <ea> is the source: Dn, An*, (An), (An)+, -(An), (d16, An), (d8, An, Xi), (d16, PC), (d8, PC, Xi), Abs.W, Abs.L, #data
 * if <ea> is the destination: (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L
 * An*: size is word or long only.


 * Flags(CCR):
 * X - contents value of C bit
 * N - 1 if result is negative, 0 otherwise
 * Z - 1 if result is zero, 0 otherwise
 * V - 1 if an overflow occurs, 0 otherwise
 * C - 1 if a carry occurs, 0 otherwise


 * Comments: the addition is binary performed. The size of the operation may be specified as byte, word or long.
 * Examples:
 * Format: 1101,3:Reg,3:OpMode,6:3Mode3Reg (16 bits, first word of the instruction)
 * Reg - the number of Dn register operand (binary codified)
 * OpMode:
 * 1st bit encodes operation order:
 * 0xx <ea> + Dn -> Dn
 * 1xx Dn + <ea> -> <ea>
 * 2nd and 3rd bits encode the operand size:
 * x00 - byte x01 - word x10 - long x11 - not used
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Integer Arithmetic │ Categories
 * OnbA use: - if you don't specify a size, .w is used by default.

 ADDA  - Adds an address


 * Adds the source operand to the destination operand.
 * Synopsis:
 * ADDA <ea>, An


 * Operands size: .w, .l
 * Source + An -> An
 * Address Modes: Dn, An, (An), (An)+, -(An), (d16, An), (d8, An, Xi), (d16, PC), (d8, PC, Xi), Abs.W, Abs.L, #data
 * Flags(CCR): not affected.
 * Comments: the addition is binary performed. The size of the operation may be specified word or long. To make it possible to mix address operations with data operations, this instruction won't affect any flag.
 * Examples:
 * Format: 1101,3:Reg,3:OpMode,6:3Mode3Reg (16 bits, first word of the instruction)
 * Reg - the number of An register operand (binary codified)
 * OpMode:
 * 011 Word operation. Operand is extended to 32 bits
 * 111 Long operation
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Integer Arithmetic │ Categories
 * OnbA use: - if you don't specify a size, .w is used by default.

ADDI - Add immediate data


 * Adds the immediate data to the destination operand.
 * Synopsis:
 * ADDI #data, <ea>


 * Operands size: .b, .w, .l
 * Data + Destination -> Destination
 * Address Modes: <ea> can be addressed using Dn, An, (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L
 * Flags(CCR):
 * X - contents value of C bit
 * N - 1 if result is negative, 0 otherwise
 * Z - 1 if result is zero, 0 otherwise
 * V - 1 if an overflow occurs, 0 otherwise
 * C - 1 if a carry occurs, 0 otherwise


 * Comments: the size of immediate data matches the operation size. Most assemblers automatically choose ADDI if the source operand to an ADD instruction is immediate. Don't forget to prefix immediate value with #.
 * Examples:
 * Format: 00000110,2:Size,6:3Mode3Reg (16 bits, first word of the instruction)
 * Size - specifies how to deal with the words following the instruction (the immediate data)
 * 00 - byte operation (the lower byte of the next word)
 * 01 - word operation (the entire next word)
 * 10 - long operation (the next two words)
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Integer Arithmetic │ Categories
 * OnbA use: - if you don't specify a size, .w is used by default.

ADDQ - Add 3-bits immediate data quick


 * Adds the 3-bits immediate data (values 1 .. 8) to the destination operand.
 * Synopsis:
 * ADDQ #data, <ea>


 * Operands size: .b, .w, .l
 * Data(3 bits) + Destination -> Destination
 * Address Modes: <ea> can be addressed using Dn, An*, (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L
 * An* - word and long only


 * Flags(CCR):
 * X - contents value of C bit
 * N - 1 if result is negative, 0 otherwise
 * Z - 1 if result is zero, 0 otherwise
 * V - 1 if an overflow occurs, 0 otherwise
 * C - 1 if a carry occurs, 0 otherwise


 * Comments: when adding to the address registers, CCR are not affected, and the entire destination address register is used regardless of the operation size. The instruction is very quick and much shorter than the usual ADD. Don't forget to prefix immediate value with #.
 * Examples:
 * Format: 0101,3:Data,0,2:Size,6:3Mode3Reg (16 bits, first word of the instruction)
 * Data
 * 000 - represent value 8
 * 001 ... 111 - values 1 to 7
 * Size - specifies how to deal with the words following the instruction (the immediate data)
 * 00 - byte operation (the lower byte of the next word)
 * 01 - word operation (the entire next word)
 * 10 - long operation (the next two words)
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Integer Arithmetic │ Categories
 * OnbA use: - if you don't specify a size, .w is used by default.

ADDX - Add integer with extend


 * Adds the source operand to the destination operand along with extend bit.
 * Synopsis:
 * ADDX Dy, Dx
 * ADDX -(Ay), -(Ax)


 * Operands size: .b, .w, .l
 * Source + Destination + CCR(X) -> Destination
 * Address Modes:
 * Data register to data register: Dn
 * Memory to memory: -(An)


 * Flags(CCR):
 * X - contents value of C bit
 * N - 1 if result is negative, 0 otherwise
 * Z - 0 if result is nonzero, unchanged otherwise
 * V - 1 if an overflow occurs, 0 otherwise
 * C - 1 if a carry occurs, 0 otherwise


 * Comments: normally the Z condition bit is set via programming before the start of an operation. That allows successful tests for zero results upon completion of multiple-precision operations. In other words, Z flag works different now, allowing to check if a big number is zero (bigger than 32 bits). You must set the zero flag before making the addition though, shorter than comparing a register with itself.
 * Format: 1101,3:Rx,1,2:Size,00,1:R/M,3:Ry
 * Rx - destination register.
 * Ry - source register.
 * R/M:
 * 0 - data register 1 - address register
 * Size
 * 00 - byte 01 - word 10 - long

A-Z Index │ Integer Arithmetic │ Categories
 * OnbA use: - if you don't specify a size, .w is used by default.

CLR - Clear operand


 * Clears an operand and sets Z flag.
 * Synopsis:
 * CLR <ea>


 * Operands size: .b, .w, .l
 * Destination -> 0
 * Address Modes: <ea> can be Dn, (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L
 * Flags(CCR):
 * X - not affected
 * N - 0
 * Z - 1
 * V - 0
 * C - 0


 * Comments: address registers cannot be cleared in this manner.
 * Examples:
 * Format: 01000010,2:Size,6:3Mode3Reg (16 bits, first word of the instruction)
 * Size
 * 00 - byte 01 - word 10 - long
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Integer Arithmetic │ Categories
 * OnbA use: - if you don't specify a size, .w is used by default.

CMP - Compare with operand


 * Subtracts without changing the destination (compares), the source operand from destination data register, and set CCR flags according to the result.
 * Synopsis:
 * CMP <ea>, Dn


 * Operands size: .b, .w, .l
 * Destination - Source -> CCR
 * Address Modes: <ea> can be Dn, An*, (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L, (d16, PC), (d8, PC, Xi), #data
 * An* - word or long only


 * Flags(CCR):
 * X - not affected
 * N - 1 if result < 0, 0 otherwise
 * Z - 1 if result == 0, 0 otherwise
 * V - 1 if overflow occurs, 0 otherwise
 * C - 1 if carry/borrow occurs, 0 otherwise


 * Comments: content of the destination data register is not changed.
 * Examples:
 * Format: 1011,3:Reg,3:OpMode,6:3Mode3Reg (16 bits, first word of the instruction)
 * Reg - one the 8 data registers
 * OpMode
 * 000 - byte 001 - word 010 - long
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Integer Arithmetic │ Categories
 * OnbA use: - if you don't specify a size, .w is used by default.

CMP2 - Compare with 2 bounds


 * Compares Rn destination with 2 lower and upper bounds stored in source.
 * Synopsis:
 * CMP2 <ea>, Rn


 * Operands size: .b, .w, .l
 * Rn ∩ Source(lower, upper) -> CCR
 * Address Modes: <ea> can be (An), (d16, An), (d8, An, Xi), Abs.W, Abs.L, (d16, PC), (d8, PC, Xi)
 * Flags(CCR):
 * X - not affected
 * N - undefined
 * Z - 1 if Rn == lower or Rn == upper, 0 otherwise
 * V - undefined
 * C - 1 if Rn < lower or Rn > upper, 0 otherwise


 * Comments: <ea> contains the bounds pair: upper bound following the lower bound. For signed comparisons, the arithmetically smaller value should be used as the lower bound. For unsigned comparisons, the logically smaller value should be the lower bound. If Rn is a data register and the operation size is byte or word, only the appropriate low-order part of Rn is checked. If Rn is an address register and the operation size is byte or word, the bounds operands are sign-extended to 32 bits, and the resultant operands are compared to the full 32 bits of An. If the upper bound equals the lower bound, the valid range is a single value.
 * Format: 00000,2:Size,011,6:3Mode3Reg (16 bits, first word of the instruction) + 1:d/a,3:Reg,000000000000
 * Size
 * 00 - byte 01 - word 10 - long
 * Reg - one the 8 registers specified by d/a
 * d/a - type of the registers
 * 0 - data 1 - address
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Integer Arithmetic │ Categories
 * OnbA use: - not implemented.

CMPA - Compare address


 * Subtracts without changing the destination (compares), the source operand from destination address register, and set CCR flags according to the result.
 * Synopsis:
 * CMPA <ea>, An


 * Operands size: .w, .l
 * Destination - Source -> CCR
 * Address Modes: <ea> can be Dn, An, (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L, (d16, PC), (d8, PC, Xi), #data
 * Flags(CCR):
 * X - not affected
 * N - 1 if result < 0, 0 otherwise
 * Z - 1 if result == 0, 0 otherwise
 * V - 1 if overflow occurs, 0 otherwise
 * C - 1 if borrow occurs, 0 otherwise


 * Comments: the content of destination address register is not changed. Word size source operands are sign extended to long for comparison.
 * Format: 1011,3:Reg,3:OpMode,6:3Mode3Reg (16 bits, first word of the instruction)
 * Reg
 * OpMode
 * 011 - word 111 - long
 * Reg - one the 8 address registers
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Integer Arithmetic │ Categories
 * OnbA use: - not implemented.

CMPI -

CMPM -

DIVS -

DIVU -

EXT -

MULS -

MULU -

NEG -

NEGX -

SUB -

SUBA -

SUBI -

SUBQ -

SUBX -

Bit Manipulation
A-Z Index │ Categories │ TOP
 * BTST - tests a bit
 * BCHG - tests and inverts a bit
 * BCLR - tests and clears a bit (to 0)
 * BSET - tests and sets a bit (to 1)
 * TAS - tests and operand and sets a bit

BCHG - Bit change


 * Test a bit in the destination operand and set Z flag appropriately, then inverts the bit in destination.
 * Synopsis:
 * BCHG Dn, <ea>
 * BCHG #data, <ea>


 * Operands size: .b, .l
 * Destination[bit] ? -> CCR(Z); Destination[bit] = ~Destination[bit]
 * Address Modes: <ea> can be addressed using Dn*, (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L
 * Dn* - long only for register; for other modes byte only.


 * Flags(CCR):
 * X - not affected
 * N - not affected
 * Z - 1 if Destination[bit] == 0, 0 otherwise
 * V - not affected
 * C - not affected


 * Comments: if the destination is a data register, any of its 32 bits can be specified (32 modulo value). When the destination is a memory location, the operation must be a byte operation, and therefore the bit number is modulo 8. In all cases bit 0 of the operand is the least significant bit.
 * Examples:
 * Format:
 * for register: 0000,3:Reg,101,6:3Mode3Reg (16 bits, first word of the instruction)
 * Reg - one of the 8 data registers
 * for immediate data: 0000100001,6:3Mode3Reg (16 bits, first word of the instruction)
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Bit Manipulation │ Categories
 * OnbA use: - No need for size specification.

BCLR - Bit clear


 * Test a bit in the destination operand and set Z flag appropriately, then clears the bit in destination.
 * Synopsis:
 * BCLR Dn, <ea>
 * BCLR #data, <ea>


 * Operands size: .b, .l
 * Destination[bit] ? -> CCR(Z); Destination[bit] = 0
 * Address Modes: <ea> can be addressed using Dn*, (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L
 * Dn* - long only for register; for other modes byte only.


 * Flags(CCR):
 * X - not affected
 * N - not affected
 * Z - 1 if Destination[bit] == 0, 0 otherwise
 * V - not affected
 * C - not affected


 * Comments: if the destination is a data register, any of its 32 bits can be specified (32 modulo value). When the destination is a memory location, the operation must be a byte operation, and therefore the bit number is modulo 8. In all cases bit 0 of the operand is the least significant bit.
 * Examples:
 * Format:
 * for register: 0000,3:Reg,110,6:3Mode3Reg (16 bits, first word of the instruction)
 * Reg - one of the 8 data registers
 * for immediate data: 0000100010,6:3Mode3Reg (16 bits, first word of the instruction)
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Bit Manipulation │ Categories
 * OnbA use: - No need for size specification.

BSET - Bit set


 * Test a bit in the destination operand and set Z flag appropriately, then clears the bit in destination.
 * Synopsis:
 * BSET Dn, <ea>
 * BSET #data, <ea>


 * Operands size: .b, .l
 * Destination[bit] ? -> CCR(Z); Destination[bit] = 1
 * Address Modes: <ea> can be addressed using Dn*, (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L
 * Dn* - long only for register; for other modes byte only.


 * Flags(CCR):
 * X - not affected
 * N - not affected
 * Z - 1 if Destination[bit] == 0, 0 otherwise
 * V - not affected
 * C - not affected


 * Comments: if the destination is a data register, any of its 32 bits can be specified (32 modulo value). When the destination is a memory location, the operation must be a byte operation, and therefore the bit number is modulo 8. In all cases bit 0 of the operand is the least significant bit.
 * Examples:
 * Format:
 * for register: 0000,3:Reg,111,6:3Mode3Reg (16 bits, first word of the instruction)
 * Reg - one of the 8 data registers
 * for immediate data: 0000100011,6:3Mode3Reg (16 bits, first word of the instruction)
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Bit Manipulation │ Categories
 * OnbA use: - No need for size specification.

BTST - Bit test


 * Test a bit in the destination operand and set Z flag appropriately.
 * Synopsis:
 * BTST Dn, <ea>
 * BTST #data, <ea>


 * Operands size: .b, .l
 * Destination[bit] ? -> CCR(Z)
 * Address Modes: <ea> can be addressed using Dn*, (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L
 * Dn* - long only for register; for other modes byte only.


 * Flags(CCR):
 * X - not affected
 * N - not affected
 * Z - 1 if Destination[bit] == 0, 0 otherwise
 * V - not affected
 * C - not affected


 * Comments: if the destination is a data register, any of its 32 bits can be specified (32 modulo value). When the destination is a memory location, the operation must be a byte operation, and therefore the bit number is modulo 8. In all cases bit 0 of the operand is the least significant bit.
 * Examples:
 * Format:
 * for register: 0000,3:Reg,100,6:3Mode3Reg (16 bits, first word of the instruction)
 * Reg - one of the 8 data registers
 * for immediate data: 0000100000,6:3Mode3Reg (16 bits, first word of the instruction)
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Bit Manipulation │ Categories
 * OnbA use: - No need for size specification.

TAS -

Shift and Rotation
A-Z Index │ Categories │ TOP
 * ASL*, ASR - arithmetic shift to the left / right
 * LSL, LSR - logical shift to the left / right
 * ROL, ROR - logical rotation to the left / right
 * ROXL, ROXR - logical rotation to the left / right with extend
 * SWAP - swaps the content of a register

ASL - Arithmetic shift to left


 * Arithmetically shifts the bits of the operand to the left.
 * Synopsis:
 * ASL Dx, Dy
 * ASL #data, Dy
 * ASL <ea>

<──
 * Operands size: .b, .w, .l
 * Destination << ShiftCount -> Destination

C <───── OPERAND <───── 0

│

X <─────┘
 * Address Modes: <ea> supported mode are (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L
 * Flags(CCR):
 * X - is set according with the last bit shifted out of the operand. Not affected if ShifCount == 0
 * N - 1 if MSBi(result) == 1, cleared otherwise
 * Z - 1 if result == 0, cleared otherwise
 * V - 1 if MSBi(result) is changed at any time during the shift operation, cleared otherwise
 * C - set according with the last bit shifted out of the operand, 0 if ShifCount == 0


 * Comments: arithmetic shift to the left can be useful as efficient ways of performing multiplication of signed integers by powers of two. The carry bit (C) receives the last bit shifted out of the operand.
 * For register shifting: shift value specified is modulo 64.
 * For immediate shifting: shift range is 1 to 8.
 * For memory shifting: an operand can be shifted one bit only, and the operand is restricted to word.


 * Format:
 * for register/immediate 1110,3:Nr/Reg,0,2:Size,1:i/r,00,3:Reg (16 bits, first word of the instruction)
 * for memory 1110000011,6:3Mode3Reg (16 bits, first word of the instruction)
 * Nr/Reg - the number of Dn register or number of shifting
 * Size
 * 00 byte operation
 * 01 word operation
 * 10 long operation
 * i/r
 * 0 - number of shifting is specified in the instruction as immediate data
 * 1 - number of shifting is specified in data register
 * Reg
 * For register shifting: indicates the number of data register on which shifting is applied.
 * For immediate shifting: indicates operand which should be shifted.
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Shift and Rotation │ Categories
 * OnbA use: - not implemented. But the counter part ASR it is. Very strange.

ASR - Arithmetic shift to right


 * Arithmetically shifts the bits of the operand to the right.
 * Synopsis:
 * ASR Dx, Dy
 * ASR #data, Dy
 * ASR <ea>

──>
 * Operands size: .b, .w, .l
 * Destination >> ShiftCount -> Destination

┌──> OPERAND ──────> C

│  │   │

└───┘  └──────> X
 * Address Modes: <ea> supported mode are (An), (An)+, -(An), (d16, An), (d8, An, Xi), Abs.W, Abs.L
 * Flags(CCR):
 * X - is set according with the last bit shifted out of the operand. Not affected if ShifCount == 0
 * N - 1 if MSBi(result) == 1, cleared otherwise
 * Z - 1 if result == 0, cleared otherwise
 * V - 1 if MSBi(result) is changed at any time during the shift operation, cleared otherwise
 * C - set according with the last bit shifted out of the operand, 0 if ShifCount == 0


 * Comments: arithmetic shift to the right can be useful as efficient ways of performing division of signed integers by powers of two. The carry bit (C) receives the last bit shifted out of the operand. Instead of being filled with all 0s, as in logical shift right, when shifting to the right, the leftmost bit (sign bit) is replicated to fill in all the vacant positions.
 * For register shifting: shift value specified is modulo 64.
 * For immediate shifting: shift range is 1 to 8.
 * For memory shifting: an operand can be shifted one bit only, and the operand is restricted to word.


 * Format:
 * for register/immediate 1110,3:Nr/Reg,0,2:Size,1:i/r,00,3:Reg (16 bits, first word of the instruction)
 * for memory 1110000011,6:3Mode3Reg (16 bits, first word of the instruction)
 * Nr/Reg - the number of Dn register or number of shifting
 * Size
 * 00 byte operation
 * 01 word operation
 * 10 long operation
 * i/r
 * 0 - number of shifting is specified in the instruction as immediate data
 * 1 - number of shifting is specified in data register
 * Reg
 * For register shifting: indicates the number of data register on which shifting is applied.
 * For immediate shifting: indicates operand which should be shifted.
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Shift and Rotation │ Categories
 * OnbA use: - if you don't specify a size, .w is used by default. The counter part ASL is not implemented. Very strange.

LSL -

LSR -

ROL -

ROLX -

ROR -

RORX -

SWAP -

BCD Arithmetic
A-Z Index │ Categories │ TOP
 * ABCD* - adds two BCD values
 * SBCD* - subtracts two BCD values
 * NBCD* - negates a BCD value

 ABCD  - Adds Binary Coded Decimal values


 * Adds the source operand to the destination operand along with extend bit.
 * Synopsis:
 * ABCD Dy, Dx
 * ABCD -(Ay), -(Ax)


 * Operands size: .b
 * SourceBCD + DestinationBCD + CCR(X) -> DestinationBCD
 * Address Modes:
 * Data register to data register: Dn
 * Memory to memory: -(An)


 * Flags(CCR):
 * X - contents value of C bit
 * N - undefined
 * Z - 0 if result is nonzero, unchanged otherwise
 * V - undefined
 * C - 1 if a decimal carry occurs, 0 otherwise


 * Comments: the addition is performed using binary coded decimal arithmetic. This operation is a byte operation only. When you add BCD numbers stored in many bytes, you must start at the highest address (the LSB in the BCD number) an go upwards. The X flag is set if the addition results in a carry, which is added to the next byte.
 * Format: 1100,3:Rx,10000,1:R/M,3:Ry
 * Rx - destination register.
 * Ry - source register.
 * R/M:
 * 0 - data register
 * 1 - address register

A-Z Index │ BCD Arithmetic │ Categories
 * OnbA use: - not supported.

NBCD -

SBCD -

Program Control
A-Z Index │ Categories │ TOP
 * Bcc, BRA - conditional branches
 * DBcc - conditional loops
 * Scc - conditional sets/clears a byte
 * BSR, JSR - procedures calls
 * RTS - return from a procedure
 * JMP - absolute jump
 * RTR - restore PC and CCR from the stack
 * TST - tests an operand for 0

Bcc - Branch if condition code


 * Branch to a label if certain flags are set.
 * Synopsis:
 * Bcc


 * Operands size: .b, .w
 * if cc == TRUE branch to
 * PC + offset(label) -> PC
 * Address Modes: Abs.W, Abs.L
 * Flags(CCR): not affected.
 * Comments: if condition code is true then program execution continues at PC + offset of the label. Offset, signed value, is the relative value in bytes which separates the Bcc instruction of mentioned label. It not need a special address method. You specify a label, which the compile will change to a relative address, byte or word, depending on how far you will jump.
 * Examples:
 * Format: 0110,4:cc,8:offset
 * cc field values:


 * offset specifies the size of offset operand, used to address :
 * $00 - a byte value for offset
 * $FF - a word value for offset

A-Z Index │ Program Control │ Categories
 * OnbA use:
 * You should not add .b or .w, the compiler will choose the best syntax for you.
 * Not implemented: BHI, BLS, BVC, BVS, BPL, BMI

BRA - Branch always


 * Branch always to a label.
 * Synopsis:
 * BRA


 * Operands size: .b, .w
 * PC + offset(label) -> PC
 * Address Modes: Abs.W, Abs.L
 * Flags(CCR): not affected.
 * Comments: always program execution continues at PC + offset of the label. Offset, signed value, is the relative value in bytes which separates the BRA instruction of mentioned label. It not need a special address method. You specify a label, which the compile will change to a relative address, byte or word, depending on how far you will jump.
 * Examples:
 * Format: 01100000,8:offset
 * offset specifies the size of offset operand, used to address :
 * $00 - a byte value for offset
 * $FF - a word value for offset

A-Z Index │ Program Control │ Categories
 * OnbA use: You should not add .b or .w, the compiler will choose the best syntax for you.

BSR - Branch to subroutine


 * Push the address (long) immediately following the BSR instruction on the stack, then branch to subroutine.
 * Synopsis:
 * BSR label(PC)


 * Operands size: .b, .w
 * SP - 4 -> SP, (PC) -> SP
 * PC + offset(label) -> PC
 * Address Modes: Abs.W, Abs.L
 * Flags(CCR): not affected.
 * Comments: program execution continues at PC + offset of the label. Label is referred by PC register. Offset, signed value, is the relative value in bytes which separates the BSR instruction of mentioned label. It not need a special address method. You specify a label, which the compile will change to a relative address, byte or word, depending on how far you will jump.
 * Format: 01100001,8:offset
 * offset specifies the size of offset operand, used to address :
 * $00 - a byte value for offset
 * $FF - a word value for offset

A-Z Index │ Program Control │ Categories
 * OnbA use: not implemented.

DBcc -

JMP -

JSR - Jump to subroutine


 * Push the address (long) immediately following the JSR instruction onto the stack, then jump to subroutine.
 * Synopsis:
 * JSR <ea>


 * Operands size: n/a
 * SP - 4 -> SP, (PC) -> SP
 * PC + <ea> -> PC
 * Address Modes: (An), (d16, An), (d8, An, Xi), (d16, PC), (d8, PC, Xi), Abs.W, Abs.L
 * Flags(CCR): not affected.
 * Comments: program execution continues at PC + <ea>.
 * Examples:
 * Format: 0100111010,6:3Mode3Reg (16 bits, first word of the instruction)
 * 3Mode3Reg - codifies address modes of the <ea>; see the table above.

A-Z Index │ Program Control │ Categories
 * OnbA use: not implemented.

RTR -

RTS -

Scc -

TST -

System Control
A-Z Index │ Categories │ TOP
 * MOVE from USP, MOVE to USP - user access of USP
 * CHK, CHK2, TRAPV - working with overflows
 * ILLEGAL - generate a vector #4 exception
 * NOP - no operation, pipelines synchronization
 * RESET - reset peripherals
 * RTE - return from an exception
 * STOP - stop and wait for an interrupt
 * TRAP - call system vectors

CHK -

CHK2 -

ILLEGAL -

MOVE from USP -

MOVE to USP -

NOP -

RESET -

RTE -

STOP -

TRAP -

TRAPV -

CCR and SR
A-Z Index │ Categories │ TOP
 * MOVE from CCR*, MOVE to CCR* - moves data to/from CCR
 * ANDI to CCR*, EORI to CCR*, ORI to CCR* - logical immediate AND/OR/EOR to CCR
 * MOVE from SR*, MOVE to SR* - moves data to/from SR
 * ANDI to SR*, EORI to SR*, ORI to SR* - logical immediate AND/OR/EOR to SR

ANDI to CCR - logical AND immediate to CCR


 * Perform a bit-wise AND operation with the immediate data and CCR as destination and stores the result in the CCR.
 * Synopsis:
 * ANDI #data, CCR


 * Operands size: .b
 * Immediate Data & CCR -> CCR
 * Address Modes: CCR
 * Flags(CCR):
 * X - 0 if Immediate Data[4] == 0, unchanged otherwise
 * N - 0 if Immediate Data[3] == 0, unchanged otherwise
 * Z - 0 if Immediate Data[2] == 0, unchanged otherwise
 * V - 0 if Immediate Data[1] == 0, unchanged otherwise
 * C - 0 if Immediate Data[0] == 0, unchanged otherwise

A-Z Index - CCR and SR │ Categories
 * Comments: the size of immediate data must be a byte.
 * Format: 0000001000111100 (16 bits, first word of the instruction)
 * OnbA use: - not implemented. (ccr or CCR syntax not recognized by OnbA)

ANDI to SR - logical AND immediate to SR


 * Perform a bit-wise AND operation with the immediate data and SR as destination and stores the result in the SR.
 * Synopsis:
 * ANDI #data, SR


 * Operands size: .b
 * Immediate Data & SR -> SR
 * Address Modes: SR
 * Flags(CCR):
 * X - 0 if Immediate Data[4] == 0, unchanged otherwise
 * N - 0 if Immediate Data[3] == 0, unchanged otherwise
 * Z - 0 if Immediate Data[2] == 0, unchanged otherwise
 * V - 0 if Immediate Data[1] == 0, unchanged otherwise
 * C - 0 if Immediate Data[0] == 0, unchanged otherwise

A-Z Index │ CCR and SR │ Categories
 * Comments: the size of immediate data must be a word. All bits of status register are affected. When execute a SR instruction you must set the S-bit (bit 13) first.
 * Format: 0000001001111100 (16 bits, first word of the instruction)
 * OnbA use: - not implemented. (sr or SR syntax not recognized by OnbA)

EORI to CCR -

EORI to SR -

MOVE from CCR -

MOVE to CCR -

MOVE from SR -

MOVE to SR -

ORI to CCR -

ORI to SR -

A-Z Index
Categories │ TOP
 * ABCD*, ADD, ADDA, ADDI, ADDQ, ADDX, AND, ANDI, ANDI to CCR*, ANDI to SR*, ASL*, ASR,
 * Bcc, BCHG, BCLR, BRA, BSET, BSR, BTST,
 * CHK, CHK2, CLR, CMP, CMP2*, CMPA*, CMPI, CMPM*, DBcc,
 * DIVS, DIVU,
 * EOR, EORI, EORI to CCR*, EORI to SR*, EXG*, EXT,
 * ILLEGAL,
 * JMP,
 * LEA, LINK, LSL, LSR,
 * MOVE, MOVEA, MOVEM, MOVEP*, MOVEQ, MOVE from CCR*, MOVE to CCR*, MOVE from SR*, MOVE to SR*, MOVE from USP, MOVE to USP, MULS, MULU,
 * NBCD*, NEG, NEGX, NOP, NOT,
 * OR, ORI, ORI to CCR*, ORI to SR*,
 * PEA,
 * RESET, ROL, ROLX, ROR, RORX, RTE, RTR, RTS,
 * SBCD*, Scc, STOP, SUB, SUBA, SUBI, SUBQ, SUBX,
 * TAS, TRAP, TRAPV, TST,
 * UNLK