Talk:VHDL for FPGA Design/D Flip Flop

Asynchronous signals must be taken into account in the sensitive list. Asynchronous signals are tested first

process (clk) is                        process (clk,rst,pre) is      -- The asyncronus signals too begin                                  begin if rising_edge(clk) then                 if (rst='1') then      -- First asyncronus signals if (rst='1') then                       q <= '0'; q <= '0';                          elsif (pre='1') then elsif (pre='1') then                    q <= '1'; q <= '1';                          elsif rising_edge(clk) then   -- syncronus signals elsif (ce='1') then                      if (ce='1') then if (d ='1') then                        if (d ='1') then q <= '1';                                  q <= '1'; elsif (d ='0') then                        elsif (d ='0') then q<= '0';                                   q<= '0'; end if;                                 end if; end if;                                  end if; end if;                                  end if; end process;                          end process; end architecture Behavioral;         end architecture Behavioral;