Talk:VHDL for FPGA Design/4-Bit ALU

4 bit alu by DIP SINGHA
DESIGN OF A FOUR BIT ALU

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

Uncomment the following library declaration if instantiating any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity comb is   Port ( a : in std_logic_vector(3 downto 0);           b : in std_logic_vector(3 downto 0);           y : out std_logic_vector(3 downto 0);           w : in std_logic_vector(2 downto 0);           ac: out std_logic;           sin: out std_logic;           cy : out std_logic;           z : out std_logic;           p : out std_logic); end comb;

architecture Behavioral of comb is signal c1,c2,c3:std_logic; signal s:std_logic_vector(3 downto 0); begin process (a,b,w,c1,c2,c3,s) variable zi:std_logic; variable aci:std_logic; variable sini:std_logic; begin p<='0'; cy<='0'; z<='0'; ac<='0'; sin<='0'; case w is when "000" =>

s(0)<=a(0) xor b(0); c1<=a(0) and b(0); s(1)<=a(1) xor b(1) xor c1; c2<=(a(1) and b(1)) or (b(1) and c1) or (c1 and a(1)); s(2)<=a(2) xor b(2) xor c2; c3<=(a(2) and b(2)) or (b(2) and c2) or (c2 and a(2)); s(3)<=a(3) xor b(3) xor c3; cy<=(a(3) and b(3)) or (b(3) and c3) or (c3 and a(3)); y<=s; p<=not(((s(0) xor s(1)) xor s(2)) xor s(3)); if s="0000" then zi:='1'; else zi:='0'; end if; z<=zi; if c2='1' then ac<='1'; else ac<='0'; end if;

when "001" =>

s(0)<=a(0) xor b(0); c1<=(not (a(0)) and b(0)); s(1)<=a(1) xor b(1) xor c1; c2<=(c1 and not(a(1) xor b(1))) or (not a(1) and b(1)); s(2)<=a(2) xor b(2) xor c2; c3<=(c2 and not(a(2) xor b(2))) or (not a(2) and b(2)); s(3)<=a(3) xor b(3) xor c3; cy<=(c3 and not(a(3) xor b(3))) or (not a(3) and b(3)); y<=s; p<=not(((s(0) xor s(1)) xor s(2)) xor s(3)); if s="0000" then zi:='1'; else zi:='0'; end if; z<=zi; if c2='1' then ac<='1'; else ac<='0'; end if; if a

y<=not a;

when "011" =>

y<=a and b;

when "100" =>

y<=a or b;

when "101" =>

y<=a xor b;

when "110" =>

s<=a+"0001"; if(a="1111") then cy<='1'; else cy<='0'; end if; y<=s; p<=not(((s(0) xor s(1)) xor s(2)) xor s(3)); if s="0000" then zi:='1'; else zi:='0'; end if; z<=zi; if (a="0011") then aci:='1'; elsif (a="0111") then aci:='1'; elsif (a="1011") then aci:='1'; elsif (a="1111") then aci:='1'; else aci:='0'; end if; ac<=aci;

when others =>

s<=a-"0001"; y<=s; if(a="0000") then cy<='1'; else cy<='0'; end if; p<=not(((s(0) xor s(1)) xor s(2)) xor s(3)); if s="0000" then zi:='1'; else zi:='0'; end if; z<=zi; if (a="0000") then aci:='1'; elsif (a="0100") then aci:='1'; elsif (a="1000") then aci:='1'; elsif (a="1100") then aci:='1'; else aci:='0'; end if; ac<=aci; if a="0000" then sini:='1'; else sini:='0'; end if; sin<=sini;

end case; end process; end Behavioral;