Talk:Programmable Logic/Verilog Control Structures

Do we want to use Verilog for examples of each code structure? If we do, then the example for 'if-else' is wrong and should be changed.

This is a bit short. I in particular miss an explanation how to break from the control loops. A notion that blocks can be named is missing and then "disable" allows quitting early. And please always mention if something can be synthesized or not. The page could also give a quick reference to $finish and $stop. smoe. Update: I addressed some core description. Please help.Smoe (discuss • contribs) 20:21, 7 September 2012 (UTC)