Talk:Programmable Logic/VHDL Module Structure

Generics for sizing and use of Unconstrained std_logic_vectors
You might want to add some details on defining modules with generics for defining things like std_logic_vector bus widths, and on doing modules with unconstrained SLVs. Unconstrained SLVs can get their width from the width of the SLV connected to them upon instantiation. Both methods are handy for creating modules with adjustable sizes (register widths, counter sizes, etc) that can be set at instantiation, or even with a top-level design generic that is passed down. Let me know if you need some examples. What do you think? --jwilkinson 20:27, 9 November 2007 (UTC)