Talk:Programmable Logic/VHDL Coding and Project Style

Coding Style - naming signals

I've seen sources where every signal is "tagged" as a signal, e.g. some_signal_s.

Since the majority of identifiers used in VHDL are signals, this seems redundant to me. If you mark the exceptions (constants, variables, ...) what else than a signal should it be? It's a bit like tagging every variable as a variable when programming in e.g. C.

Sid6p8 (discuss • contribs) 08:41, 12 November 2014 (UTC)