Talk:Make

Makefile templates
May I suggest a section (or sub page) with complete Makefile templates for typical projects? There are examples of a small c++ project, but it should be nice with for instance VHDL projects, LaTeX projects etcetera. --Petter Källström, 78.69.195.202 (talk) 12:55, 12 August 2010 (UTC)
 * No one complained for over 4 months, so I created the page Make/Examples, with only a LaTeX Makefile example. Worth to link to from the original article? --Petter Källström, 130.236.56.173 (talk) 17:12, 23 December 2010 (UTC)

Questions
A question (so far):

Looping directives
I have a list (e.g. a variable containing all my .o files), and I would like to generate one rule for each of them. Something like: Foreach file, $(ObjFiles) $(file).o : $(file).cpp $(COMP) $@ endforeach This should be possible using the $(foreach ., ., .) function, if you can accept to generate another makefile each time that you call. Is there any simpler way? -- Petter Källström, again. 130.236.56.173 (talk) 16:13, 21 December 2010 (UTC)


 * Yes, there's a simpler way -- "implicit rules". In particular, "built-in implicit rules" make this super-easy.


 * This particular task you mention is super-common: "I have a bunch of ".cpp" files, and each one needs to be compiled into its respective ".o" intermediate files before I link them all together into the final executable (unless somehow I can automatically skip some particular compilation because I haven't changed that ".cpp" since the last time I made the ".o" file from it)".


 * The particular task you mention is so super-common that there is a built-in implicit rule to recent versions of make to handle it.
 * When you type "make" on the command line and it finds the following makefile:


 * then "make" automagically hunts around for some source file "file2.c" or "file2.cpp" or "file2.p" or "file2.f" source file it can possibly compile to create that "file2.o" file, then re-builds "file2.o" from whichever one of those files it found, using the appropriate compiler and the appropriate compiler flags.
 * This may at first appear to be merely a fragment of a makefile that *only* handles one step -- it appears to *only* run "g++" once, converting the penultimate ".o" intermediate files into the final ".file" executable -- but this file is actually so much more.
 * This is a complete makefile that handles the complete process of converting several source files (and creating a bunch of ".o" files as an intermediate step) into the final "file1" executable.
 * (If you don't like the built-in defaults, the Catalogue of Rules explains how to set the appropriate C compiler, C++ compiler, Pascal compiler, and Fortran compiler, and how to set the appropriate compiler flags for each one).
 * How can we improve the make Wikibook, so when it mentions that makefile, our readers understand that it's a complete makefile that handles the complete process, rather than just a fragment of a makefile that handles one step of the process?


 * The more general task you mention -- "I have a long list of input source files, and I want to run some function on each one of them, as if I manually typed in a separate rule like this for each one of them -- but, alas, there is no built-in implicit rule to handle this kind of file" -- can also be handled by a single implicit rule, but it's more complicated.
 * Adding the following lines to your makefile would define an implicit rule to handle the files you mentioned in your example (if, hypothetically, this was not already a built-in implicit rule):


 * Should we explain implicit rules in detail in this Wikibook, or is it enough to briefly mention them as an advanced topic and link to Using Implicit Rules ? --DavidCary (discuss • contribs) 15:39, 25 October 2011 (UTC)

A joke
This joke may or may not be appropriate for the text. But my advice when learning a new programming language "Fake it till you make it."