Talk:Digital Circuits/Adders

Thanks, very clear and helpful. Could somebody do the missing bits? Chendy (talk) 22:55, 31 May 2009 (UTC)

Why is the total propagation delay as 6 for the lookahead adder?
After the carries are generated (in 3 cycles), they only need to go through an additional XOR gate, giving a total of 4 gate delays to generate the sum. Can someone explain how the following was calculated?

Produce sum result, S 	Carry signals and addends 	3