Talk:Circuit Idea/Revealing the Truth about ECL Circuits

I have started the discussion about ECL by moving my insertions from the related Wikipedia page. Circuit-fantasist (talk) 10:43, 5 November 2009 (UTC)

ECL operation
To answer the questions above, please let me scrutinize the circuit operation. Maybe, you will get bored but I suggest to do that once and for all to reach consensus on how ECL operates. After that we may draw final conclusions. To make my detailed explanations more concrete and to link them to the picture, I will try to determine roughly the circuit parameters as wells. Let's assume we investigate an ECL inverter: the input voltage is applied to T1's base and T2's input is unused (T2 does not exist). Assume also the circuit has low voltage threshold VL = -1.7 V and high voltage threshold VH = -0.9 V that are situated symmetrically (±0.4 V) with respect to the reference voltage VREF = -1.3 V. Circuit dreamer

Below the low voltage threshold
(this situation will never occur if the circuit is driven by another identical ECL circuit; it will occur only if the circuit is driven by an input voltage source with lower voltage than the low voltage threshold).

Imagine the input voltage has got down vastly below the low voltage threshold VL (e.g., we have connected T1 base to VEE = -5.2 V). At this stage, think of the voltage divider R1-R2 and the emitter follower T3 as of a voltage source (voltage stabilizer) that fixes T1 emitter voltage at VE = VB3 - VBE3 = -1.3 - 0.7 = -2 V. As a result, T1 base-emitter junction becomes backward biased (VBE1 = VCC - VE = -5.2 + 2 = -3.2 V); T1 is cut off and its collector voltage is almost 0 V. If we continue decreasing the input voltage, at given point a zener breakdown will occur.

In this state, the circuit does not consume a current from the previous stage since T1 base-emitter voltage is less than the cut-in voltage or T1 base-emitter junction is backward biased. So, the input resistance is extremely high.

Low input voltage (logical "0")
(there is no picture for this case)

Left part. Now imagine our circuit is driven by another identical ECL circuit whose output stage (the emitter follower T5') has placed low input voltage VL = -1.7 V at T1 base. Its base-emitter voltage is VBE1 = VL - VE = -1.7 + 2 = 0.3 V; T1 is cut off and its collector voltage is almost 0 V.The T4 base current flows through RC1 and creates only a small voltage drop about VRc1 = 0.2 V. So, the output voltage VY = 0 - VRc1 - VBE4 = -0.2 - 0.7 = -0.9 V (logical 1") and does not depend on the gate input voltage. The left part of the long-tailed pair is disconnected from the right part and does not affect it.

In this state, the circuit does not consume a current from the previous stage since T1 base-emitter voltage is less than the cut-in voltage. So, the input resistance is high.

Right part. Now, think of the voltage divider R1-R2, the emitter follower T3 and the emitter resistor RE as a current source passing a current IC3 = (VR2 + 2VF - VBE3)/RE through the T3 collector resistor RC3 (this current will determine the maximum T1 collector current in the next state when it will be steered to flow through T1; so, it has to be lower than T1 saturation current to prevent saturation). Or, if you prefer, think of the combination RE, T3 and RC3 as of a common-emitter amplifier (actually, it is not an amplifier but an attenuator with K = Rc3/Re < 1) with emitter degeneration driven by the constant voltage VREF = VR2 + 2VF. The resistance RC3 (245 Ω) is chosen so that, at the reference input voltage VB3 = -1.3 V, the T3 collector current to create voltage drop VRc3 = 1 V across it. So, the output voltage VY = 0 - VRc3 - VBE5 = 0 - 1 - 0.7 = -1.7 V (logical "0"). The voltage drop across T3 (VCE3 = VC3 - VE = -1 + 2 = 1 V) is high enough to keep T3 in the active region. The output voltage depends on the resistances RE, RC3, R1 and R2 and will vary if they vary. But these variations will not accumulate after next several stages since the input transistor T1 (T2) of the next ECL gate will be cut off and its collector voltage (accordingly, the output voltage VY) will not depend on the gate input voltage. T3 collector voltage (accordingly, the output voltage VY) of the next gate will not depend on the gate input voltage as well; it will depend on its reference voltage.

Low-to-high transition
(scrutinizing the current steering idea)

Now imagine the input voltage begins rising over the low treshold VL = -1.7 V. T1 begins opening; it increases its emitter current and voltage drop across RE. Figuratively speaking, T1 begins "pulling up" T3 emitter:) thus closing gradually T3 and taking bit by bit its current. The situation is very interesting and it is worth to be generalized as other legendary circuits (e.g., common-base amplifying stage) are based on the same idea.

During the transition, two voltage sources (more precisely, two voltage-stable elements) are connected in parallel (T1 emitter follower from the left side and T3 emitter follower from the right side) and are supplied by a common current source (the emitter resistor RE supplied by VEE). Figuratively speaking, the two voltage sources are in conflict:) as the right voltage source does its best to keep a steady emitter voltage while the left voltage source tries to increase it. Note these voltage sources are negative feedback systems that react to any intervention applied to their outputs. So, when T1 begins opening to increase its emitter current and emitter voltage, as an answer, T3 begins closing to lower its emitter current and accordingly to decrease the emitter voltage. As a result, the collector current redirects (fades) rapidly from the right to the left side at approximately constant emitter voltage.

During the middle of transition the input resistance is low since the circuit behaves as a common-emitter stage with relatively steady emitter voltage.

This evening, my colleague V. Mollov made a SPICE simulation and we observed how the two collector currents were changing during the transition. At the middle area, the two currents change (fade) rapidly. Approaching the high threshold VH = -0.7 V, T3 collector current becomes almost zero while T1 collector current begins changing slowly. How do we explain this behavior? Let's try answering this question.

During the transition, the right (reference) emitter follower T3 is connected to T1 emitter and fixes its voltage (makes it "stiff", "hard", stable...) Figuratively speaking, the reference emitter follower T3 shorts the emitter resistance during the transition. So, there is no negative feedback in the input stage and it acts almost as a CE amplifier with high gain (transconductance G). At the end of the transition, the reference emitter follower T3 "unhooks" from T1 emitter; the emitter resistor "appears" and introduces a series negative feedback (the so-called emitter degeneration). The input stage already acts as a real CC amplifier (emitter follower) with "soft" emitter voltage that follows the input one. As a result, the T1 collector current becomes IC1 = IRE = (VIN - VBE1)/RE and its curve begins loosing its nerve:) Accordingly, VC1 and VY continues changing slowly ( Y 's logical "0" depends slightly on the input voltage). Note there is no such a problem with T3 collector current in the beginning of transition as it is set by the steady reference voltage (Y's logical "0" does not depend on the input voltage).

At the end of the transistion, when the input voltage reaches the high threshold VH = -0.7 V, all the T3 collector current is taken by T1. This is its maximum collector current that is lower than its saturation current ISAT = VEE/(RC1 + RE) and T1 is prevented against saturation. Note 'the final collector current does not depend on T1's β (on particualar transistor). It depends only on VEE, RE and RC1 and this is the benefit of using the powerful current steering idea here!'

If we are curoius and penetrative enough, we may see the same trick (connecting in parallel two voltage-stable elements with different thresholds to redirect the current to the element with the lower threshold) in many other circuits. For example, when we ground a TTL (or DTL) input, we connect one base-emitter junction (of the multiple-emitter transistor) in parallel to two series-connected junctions (the base-collector junction of the multiple-emitter transistor and the base-emitter junction of the second transistor); as a result, the input single junction sinks all the base curent. The same trick is applied in the TTL totem-pole output stage where, at output logical "0", the transistor V2 connects the V4 base-emitter junction in parallel to the series-connected V3 base-emitter junction and deliberately inserted V5 junction; as a result, the single V4 base-emitter junction deprives all the V3 base curent. This trick can be easily demonstrated by connecting in parallel different LEDs as they show where current flows and how big they are without connecting an ammeter. A month ago, in the beginning of TTL labs, I made my students conduct this extremely simple but very attractive experiment in the laboratory. I scаttered handful of different colored LEDs and made students connect consecutively a 2 V red LED to the same 2 V red (green, yellow) LED, then to a 3 V blue LED and finally, to a composed 4 V "LED" (two connected in series 2 V red LEDs). They were deeply impressed when saw how the single red LED extinguished LEDs or combination of LEDs having higher forward voltage. BTW, in 1983, I invented and patented maybe the simplest zero voltage LED indicator (- 0 +) containing only two transistors, two resistors and, of course, three LEDs (one green and two red). Later, I developed this idea to linear and 2-dimensional LED indicators (I managed to patent the latter). If you show interest in these clever circuits, I will show them to you; for now, I give an opportunity to you to disclose their mistery:) Circuit dreamer (talk) 07:28, 23 October 2009 (UTC)

High input voltage (logical "1")
See the picture (there is a little mistake - VCE3 is actually VC3).

Left part. The preceding output stage (the emitter follower T5') has already set high input voltage VH = -0.9 V at T1 base. As above, you may think of the emitter follower T1 and the emitter resistor RE as a voltage-controlled current source (voltage-to-current converter or a transconductance amplifier) passing a current IC1 = (VRE5' - VBE1)/RE through the collector resistor RC1. Or you may think again of the combination RE, T1 and RC1 as of a common-emitter amplifier (as above, it is sooner an attenuator with K = Rc1/Re < 1) with emitter degeneration driven by the constant voltage VRE5'. The resistance RC1 (220 Ω) is chosen so that, at high input voltage VIN = VH = 0.9 V, the T1 collector current to create voltage drop VRc1 = 1 V across it. So, the output voltage VY = 0 - VRc1 - VBE4 = 0 - 1 - 0.7 = -1.7 V (logical "0"). The voltage drop across T1 is VCE1 = VC1 - VE = - 1 + 1.6 = 0.6 V and the transistor is still not saturated. The output voltage depends on the resistances RE, RC1 and the input voltage VIN; so, it will vary if they vary. As Rc1/Re = 0.22 the output voltage depends slightly on the input voltage (it won't depend at all if we replace RE by a constant current source). But again, as above, these variations will not accumulate after next several stages since the input transistor T1 (T2) of the next ECL gate will be cut off and its collector voltage (accordingly, the output voltage VY) will not depend on the gate input voltage. T3 collector voltage (accordingly, the output voltage VY) of the next gate will not depend on the gate input voltage as well; it will depend on its reference voltage. Circuit dreamer (talk) 10:00, 23 October 2009 (UTC)

At this stage, the input resistance becomes very high since the circuit begins acting as emitter follower (common-collector stage).

Right part. At this point, the input emitter follower T1 has "pulled-up" the T3 emitter to a level of VE = -1.6 V. As a result, the base-emitter voltage of T3 is VBE3 = VB3 - VE = -1.3 + 1.6 = 0.3 V; so, T3 is cut off and its collector voltage is almost 0 V. Only the T5 base current flows through RC3 and creates small voltage drop about VRc3 = 0.2 V. So, the output voltage VY = 0 - VRc3 - VBE5 = -0.2 - 0.7 = -0.9 V (logical 1") and does not depend on the gate input voltage. The right part of the long-tailed pair is disconnected from the left part and does not affect it.

Above the high voltage threshold
(this situation will never occur if the circuit is driven by the same ECL circuit; it will occur only if the circuit is driven by an input voltage source with higher voltage than the high voltage threshold).

If we continue increasing the input voltage above this level (e.g., if we connect T1 base to ground or to a positive voltage source), T1 will saturate presently. The collector and emitter points join and the input voltage transfers directly through T1 base-emitter junction to this point (VY follows VIN). The input part behaves as a voltage divider; so, the input resistance becomes relatively low again (RIN = Rc1||Re).

Nevertheless, T1 continues "moving up" T3 emitter. After the point where VIN = -0.6 V, T3 base-emitter junction becomes backward biased and, at given point, a zener breakdown occurs. Circuit dreamer (talk) 12:57, 24 October 2009 (UTC)

Emitter resistors are included in the early MC306G gate and later they are omitted in the next MC307G gate (see more in Motorola MECL logic family datasheets, 1963. Circuit-fantasist (talk) 08:44, 20 October 2009 (UTC)

I agree with you and would like to add some words about the difference between an emitter coupled pair (ECP) and a differential amplifier (DA). ECP is a particualar case of DA. ECP is a partial DA operating only in a "single-input varying" mode (I'm not sure how to name this regime; "differential" is doubtful). ECP does not operate in a common mode. That is why, a bare emitter resistor can act as an almost perfect current source (as the voltage across it is almost constant). DA with single-ended output needs a perfect current source to be connected as a "tail" to suppress the output voltage variations in common mode. Circuit dreamer (old Circuit-fantasist) (talk) 22:43, 20 October 2009 (UTC)

In all the logic families, we can distinguish two main parts: an input part that implements the logical functions and an output part that boosts the weak input part. The input parts of NMOS logic, DCTL and ECL are based on the same simplest logical structure - a few connected in parallel voltage-controlled (MOS) or current-controlled (BJT) electronic switches supplied by a current source. As these switches are implemented by enhancement mode transistors (i.e., when the input voltage increases, the transistor opens) and the voltage drop across the transistors is taken as an output, this structure is inverting and performs logical NOR function. Ooh, I will not sleep again this night:) Circuit-fantasist (talk) 20:43, 20 October 2009 (UTC)

Saying "current source" I mean the combination of the voltage supply and the collector (drain) resistor that constitute a simple current source. If you prefer, you may name it "imperfect voltage source". Another wide-spread viewpoint: the pull-up resistor and the lower group of parallel-connected switches constitute a voltage divider. Saying "In many families, the input logic switches are the same transistors that drive the output..." you probably mean complementary structures (e.g., CMOS). But note I've confined only to "simple inverter" structures with pull-up resistor (ECL, DCTL and NMOS). Circuit-fantasist (talk) 21:45, 20 October 2009 (UTC)

You have made me ponder seriously... Really, I always try to arrange circuit evolution in a logical (instead historical) succession to reveal basic ideas to my students. IMO TTL and DTL (AND implementation) are relations since both they use exotic diode switches in the logical input part; TTL is an improved version of DTL (only in some respect). About complementary outputs...I can't assess how important it is. I can't realize why I try to find some relationship between different logic families regarding to the input logical part but you - regarding to the output stage... But my mind turns off and I go to bed:) Thank you for the interesting talk. Circuit dreamer (talk) 23:38, 20 October 2009 (UTC)

About the picture
I have drawn the picture and place it in Circuit operation section with the purpose to show a generalized (generic) circuit diagram of a typical ECL circuit. It differs slightly from the particular MECL 10k (the additional reference emitter follower Q4 is omitted and additional resistors are connected in the emitters of the output transistors). I have arranged uniformly the circuit components and stretched the circuit diagram so that it to fill out the drawing. Then, to visualize the invisible electrical attributes, I have overlaid a picture of voltage and current relief. In this attractive presentation, voltages and voltage drops are represented by red colored bars, whose heights are proportional to the corresponding voltage magnitudes (an association with a water column); currents are represented by green colored loops with corresponding topology and thickness that is proportional to the magnitude of the current (an association with a water flow). Having a look at this picture, we can instantly get a notion of how "high" voltages (drops) are and how they are related; we can see how big currents are and how they flow. I have been using this technique since 80's and I have been trying to popularize it... but without any success... just because I was (and still am:) nobody... In 90's, I was drawing a lot of such colorful pictures by using Corel draw editor (see for example our favorite differential amplifier but here with dynamic load). In the early 00's, when I started circuit-fantasia, I was creating a lot of such but animated presentations implementing them as Flash movies (see for example, one "serious" and one funny story that I gave to Tom Hayes). I have been even using on-line presentations where graphical voltage bar (diagram) representations are driven by the very real circuit under investigation (see for example, the story about Ohm's law). It would be very useful if simulating programs had such a graphical output... Finally, when I realized that content is more important than form, I began drawing manually such colorful pictures using only fiber pens with various colors...

I like this picture as it is informative and self-explaining. But if you think it is too ornate, I can redraw it in this manner but retaining only the essential differential part and removing some of the more inessential circuits (the previous stage, the output emitter followers or/and the reference voltage divider). In this case, I can afford to draw another picture for the case of low input voltage (logical "0"). Thus we may describe the two circuit states linking the texts to the two figures. Circuit dreamer (talk) 21:59, 24 October 2009 (UTC)



Dicklyon and Jc3s5h, thank you for your appreciation! I have a compromised solution to the problem that will satisfy both the ordinary and profound Wikipedia readers - to draw three versions of this picture with identical dimensions and then to give an opportunity to the very readers to choose the desired version. The three versions can be: The first picture will be placed in the article and two links inserted in the capture will point to the other two versions (see the exemplary figure on the right). A more sophisticated implementation may be based on dynamic HTML (mouseover effect); but I'm not sure if wiki markup supports this feature. Circuit dreamer (talk) 14:44, 25 October 2009 (UTC)
 * 1) Pure circuit diagram (without overlaid voltage bars and current loops)
 * 2) Circuit diagram with overlaid voltage bars and current loops at low input voltage (logical "0")
 * 3) Circuit diagram with overlaid voltage bars and current loops at high input voltage (logical "1")

Summarizing the key points of the discussion
I suggest to begin extracting and summarizing as final conclusions the key points of our discussion upon which we have reached some agreement. After that we may move them to the main article and to other related articles as well. I start the list with the hope that you will enrich it with more wisdom:) Circuit dreamer (talk) 17:56, 26 October 2009 (UTC)


 * Digital circuits are actually analog circuits that are made operate as digital ones at the ends of the input range. They operate as analog circuits in the transition area.


 * The simplest 1-transistor amplifying stages are inverting as they are implemented by "enhancement mode" transistors (when the input voltage increases, the collector current increases as well) and the voltage drops across their collector-emitter parts are taken as output voltages.


 * Logic gates are overdriven DC analog amplifiers without biasing. The transistors of DCTL, RTL, DTL and TTL can stay in three conditions: saturated (at logical "1"), in active regime (during the transition) or cut-off (at logical "0").


 * ECL transistors can't operate only in active regime (in both the logical "0" and logical "1" input signal) since, when cascaded, they will amplify the input voltages (the big problem); a DC drift will propagate and accumulate through the consecutively connected stages as well (the smaller problem).


 * ECL (input) transistors can stay in two conditions: in active regime (at logical 1 and in transition area) or cut-off (at logical 0). As a result, they change alternatively their condition (...active -> cut-off -> active -> cut-off...) along the chain. The cut-off transistors stop the drift by separating the output voltage from the input voltage; they replace the input voltage by the constant supply voltage (0 V).


 * These logic gates consist of two parts: an input part that implements the logical functions and an output part that boosts the weak input part.


 * DCTL and ECL have the same logical parts consisting of parallel connected electronic switches (BJT transistors with parallel connected collector-emitter parts). An ECL gate includes a DCTL gate; ECL is an improved version of DCTL in regard to saturation problems.


 * To avoid saturation, the current steering idea is used in ECL. It is implemented by a 3-component structure where a current-stable element (or just an ohmic resistor) is conected in series to two connected in parallel (voltage-controlled) voltage-stable elements. This circuit is called by the figurative and self-explaining (in regard to the structure) descriptive name "long-tailed pair".


 * In regard to usage, a long-tailed pair is named "differential amplifier", "emitter-coupled amplifier", "analog multiplier", "an amplifier with voltage-controlled gain", etc.

Revealing the truth about ECL circuits
(seeing the forest for the trees)

I am in the seventh heaven as I have finally revealed the fundamental idea of ECL... It is not differential amplifier (more precisely, emitter-coupled amplifier) or current steering although, in the middle of transition, the circuit is exactly a differential amplifier (an emitter-coupled amplifier) that steers the current between the legs. Well, I agree it steers; but imagine some curious and profound visitor like our anonymous 60.241.12.136 (see DC drift of output section above) brows through this highest Google ranked page in the hope of grasping the basic ECL idea. Reading "current steering" he/she will want to know why the emitter current is steered between the two legs; with what purpose is the current steered? Why a differential amplifier is used? What problem does it solve here? To answer these questions, we have first to show what the fundamental problem of ordinary logic circuits is and then to show how this problem is solved in ECL. I can say (and will say at the end) in a few words what this genius idea is but let me first expose it in detail as it deserves more respect. Circuit dreamer (talk) 07:47, 3 November 2009 (UTC)

The problem of saturation
Differential amplifier, emitter-coupled amplifier and current steering are misleading concepts here. They cannot explain what fundamental problem ECL has solved as they focus our attention to the middle part of transition where actually there is no any problem! In this area, the transistors of all the ordinary logic circuits (RTL, DCTL, DTL and TTL) work perfect as common-emitter stages in active regime. If we were staying in this area, there was no any need to replace them with this more sophisticated and odd 3-component structure figuratively named long-tailed pair as it would do the same - it would work as the same common-emitter stage!

A problem appears when the input voltage approaches the high threshold (logical "1") and the transistors of the ordinary logic circuits (RTL, DCTL, DTL and TTL) saturate; as a result, they work slowly. But, as our curious reader would think, the differential (emitter-coupled) amplifier couldn't solve this problem as, in this area, the reference transistor T3 is cut-off and the differential amplifier is not an amplifier. That's why, to realize what happened above, the reader has created his own "philosophy" about ECL thinking of a differential amplifier not as of an amplifier but as of a comparator. Really, the long-tailed pair is cut in two and this structure is no more a differential amplifier; its two new parts are something else. So, the paradox of this classic viewpoint is that we use a differential amplifier where actually it is not a differential amplifier!

Saturation is the fundamental problem that ECL circuits solve at high input voltage (logical "1"). This and only this is the amazing feature of ECL; the other advantages (as the presence of two inverse outputs) are inessential. So, it is our primary duty to show in this page the basic idea (the clever trick, the circuit solution, the remedy...) that is used to prevent saturation. But how can we prevent saturation? Let's see and compare various anti-saturation techniques.

How to prevent saturation:
We can drive the transistor from the side of the base and from the side of the emitter. So, we may prevent saturation indirectly from the side of the base by limiting the base current or directly from the side of the emitter by limiting the very collector current.

...from the side of the base...
We have two techniques for limiting the base current that require the presence of a base resistor (i.e., they are inappropriate for direct-coupled circuits).


 * The simplest and obvious solution is to decrease the base current by increasing the base resistance. But the large tolerances of β make this approach unrealizable as the collector current and the point of saturation will depend on the particular transistor.


 * Another but reliable and wide used β-independent technique for preventing saturation is to detract the excessive base current by a diode negative feedback (connecting a Schottky diode between the collector and the base). Until the transistor is in active mode, the diode is cut-off and does not affect the base current. When it approaches the saturation point, the diode turns on and deprives the excessive base current.

...from the side of the emitter.
Finally, we may try to avoid saturation by limiting the very collector (emitter) current and thus we will finally arrive at ECL. But we cannot set the desired emitter current in a common-emitter stage (DCTL) simply by inserting a constant current source (or, in the simpler case, an ohmic resistor) between the emitter and ground as we will not be able to control at all (or slightly, in the case of the resistor) the collector current from the base. Why? The answer is that the current source (the emitter resistor) will introduce series negative feedback and the common-emitter amplifying stage will transmute into a stage with emitter degeneration. As a result, when we change the input base voltage to change the collector current, the transistor changes in the same manner its emitter voltage and we do... nothing:( Figuratively speaking, when we "move" the base voltage, the transistor "moves" in the same manner its emitter voltage (it operates as an emitter follower). The emitter voltage has become "soft", "pliable", "movable"...; but to control the collector current the emitter voltage has to be "hard", steady, fixed...

This is a fundamental problem of analog circuit design - how to set the desired collector current (the quiescent point) without loosing control from the base. Or, in other words, how to make the emitter voltage "soft" for the undesired influences and "hard" for the useful input voltage applied to the base. Typical examples: an AC amplifier with emitter degeneration suppresses the slow DC variations and amplifies rapidly changing AC input variations; a differential transistor amplifier suppresses common-mode signals and amplifies differential input signals; finally, an ECL gate suppresses the input voltage variations near to the high threshold (input logical "1") and amplifies them significantly during the transition. It is clear that there is some common powerful idea in these apparently different circuits... What is it?

Obviously, to make the emitter voltage "soft", we have to insert a constant current source (actully, a current-stable element) and v.v., to make the emitter voltage "hard", we have to insert a constant voltage source (a voltage-stable element). Instead to replace the current source with a voltage source we may just connect the voltage source in parallel to the current source as it will define the voltage across the combination of two elements. In the first two examples above, the voltage sources are permanently connected to the current ones but they appear only at useful input signals. In the AC amplifier, the bypass emitter capacitor follows the slow DC variations and does not affect the current source; but it begins acting as a constant voltage source at rapidly changing AC input variations. In the differential amplifier, the right emitter voltage follows the left one at common-mode and does not affect the current source; but it becomes steady (or opposite changing) at single-ended (or differential) mode. In ECL gate, solely the constant current source is connected in the emitter when the input voltage is near to the high threshold (input logical "1"); both the constant current source and the constant voltage source are connected in the emitter during the transition (the sources are commutated by the transistor's base-emitter "diode switches"). Let's consider the three possible configurations.

VIN < VL, VIN = VL (logical "0"). T1 is cut off; VY = 0 V and does not depend on VIN. Both the current source (RE) and the voltage source (T3) are disconnected from the input part.

VL < VIN < VH (transition). T1 operates in active regime (common-emitter configuration) with both the parallel connected current source (RE) and voltage source (T3) inserted in its emitter. There is no negative feedback. VY depends significantly on VIN since the voltage source dominates over the current one and the T1's emitter voltage is "hard".

VIN = VH, VIN > VH (logical "1"). T3 is cut off and there is no voltage source. Only the current source (RE) is connected in T1's emitter (emitter degeneration). There is a series negative feeddback. VY = VL and does not depend at all (in the case of constant current source) or depends slightly (in the case of emitter resistor) on VIN since T1's emitter voltage is "soft".

Finally, let's say the truth about ECL with one sentence:

ECL is based on a transistor stage with switchable voltage and current emitter sources: at low input voltage, the sources are disconnected; during the transition, both the voltage and current source are connected; at high input voltage, only the current source is connected.

Circuit dreamer (talk) 20:35, 2 November 2009 (UTC)