Talk:A-level Computing 2009/AQA/Computer Components, The Stored Program Concept and the Internet/Machine Level Architecture/The Fetch–Execute cycle and the role of registers within it

This is closer than previous one but has a few problems

I will assume that the instructions create a short addressing or offset addressing mode when referencing other locations so the address and instruction can be stored in data width for one instruction fetch cycle, as other full address modes would require the instruction then the following location(s) to contain the full address that would need to be fetched as well as part of instruction decode fetch cycles.

Registers involved is missing Accumulator (ACC) description that just appears in the diagrams.

The initial diagrams are correct enough

Final diagram has mistakes

MAR = 206 (the memory address fetched) as ONE of the stages of the instruction decode, hence why different addressing modes or moving data between registers is quicker.
 * 1) It does "as if by magic" jump of missing the extra fetch cycle of fetching from memory (address 206) to MBR then execute of MBR to ACC
 * 2) Due to (1) some of the registers have WRONG contents

MBR = 1 the data fetched from 206

Depending on processor and memory organisation an instruction decode phase can involve many fetch cycles (multibyte reads) before it is executed, and the execution may involve a fetch (well actually store) cycle as well.

I dont know if the xercises is supposed to be a complete answer it is not as it starts on one instruction but finishes on second with bits missing in the middle the first three expanded sections end with the same wrong diagram

You could do with some ordered MNEMONICS to explain difference meant between LOAD 167 and LOAD #166 as experienced engineer with over 30 years on many languages and processors I know but someone new wont! Techpaul (discuss • contribs) 19:58, 13 February 2014 (UTC)


 * Hi and thanks for the feedback. Will try and tackle your points in reverse order:
 * - The previous page A-level_Computing/AQA/Computer_Components,_The_Stored_Program_Concept_and_the_Internet/Machine_Level_Architecture/Machine_code_and_processor_instruction_set covers LOAD 167 and LOAD #166, which should mean they can handle these questions.
 * - You seem correct on the MBR, this is a simplification of the process in line with the register notation. I'll look to see if we can get an easier diagram.
 * - ACC should be added to registers, do you fancy jumping in and adding a definition?
 * Thanks! Pluke (discuss • contribs) 23:32, 13 February 2014 (UTC)