Programmable Logic/VHDL General Syntax

VHDL's syntax is derived from ADA. It is strongly typed and case insensitive.

Identifiers
An identifier in VHDL must begin with a letter and can be any combination of letters, digits, and underscore (_).

Comments
A comment in VHDL is denoted with a "--": Everything after the "--" to the end of the line is considered a comment.

Keywords
The following words are VHDL keywords and cannot be used for identifiers (signal names, process names, entity names, etc...)

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VHDL 1987
This is an incomplete list...

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VHDL 1993
VHDL 1987 keywords and:

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VHDL 2000
VHDL 1993 and 1987 keywords, additionally:

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VHDL 2002
VHDL 1993, 1987 and 2000 keywords, additionally:

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VHDL 2008
VHDL 1993, 1987, 2000 and 2002 keywords, additionally:

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VHDL 2019
VHDL 1993, 1987, 2000, 2002 and 2008 keywords, additionally:

Alphabetical Reference


A
abs             access          after           alias           all             and             architecture    array          </li> <li>assert         </li> <li>attribute      </li>

B
<li>begin          </li> <li>block          </li> <li>body           </li> <li>buffer         </li> <li>bus            </li>

C
<li>case           </li> <li>component      </li> <li>configuration  </li> <li>constant       </li>

D
<li>disconnect     </li> <li>downto         </li>

E
<li>else           </li> <li>elsif          </li> <li>end            </li> <li>entity         </li> <li>exit           </li>

F
<li> file          </li> <li> for           </li> <li> function      </li>

G
<li> generate      </li> <li> generic       </li> <li> guarded       </li>

I
<li> if            </li> <li> in            </li> <li> inout         </li> <li> is            </li>

L
<li> label         </li> <li> library       </li> <li> linkage       </li> <li> loop          </li>

M
<li> map           </li> <li> mod           </li>

N
<li> nand          </li> <li> new           </li> <li> next          </li> <li> nor           </li> <li> not           </li> <li> null          </li>

O
<li> of            </li> <li> on            </li> <li> open          </li> <li> or            </li> <li> others        </li> <li> out           </li>

P
<li> package       </li> <li> port          </li> <li> procedure     </li> <li> process       </li>

R
<li> range         </li> <li> record        </li> <li> register      </li> <li> rem           </li> <li> report        </li> <li> return        </li>

S
<li> select        </li> <li> severity      </li> <li> signal        </li> <li> subtype       </li>

T
<li> then          </li> <li> to            </li> <li> transport     </li> <li> type          </li>

U
<li> units         </li> <li> until         </li> <li> use           </li>

V
<li> variable      </li>

W
<li> wait          </li> <li> when          </li> <li> while         </li> <li> with          </li>

X
<li> xor           </li>

Z
</ul>

links to other references
https://peterfab.com/ref/vhdl/vhdl_renerta/source/vhd00001.htm

abs
- The abs command in VHDL is a predefined function that returns the absolute value of a numeric argument.
 * Introduction

For example,  returns , and   returns.

The abs command can be used with any numeric type, such as integer, real, or fixed-point.

The 1987 version of VHDL saw the introduction of abs.
 * Notes

The abs command is synthesiseable.

synthesizable, Rules, tips, common mistakes, related keywords etc


 * Syntax

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access
- In VHDL, an access type is like a pointer in other programming languages. It allows you to create and manipulate data that is created dynamically during simulation. This means that you can create new data on the fly, and the size of the data doesn’t have to be known in advance.
 * Introduction

For example, imagine you want to create a list of numbers, but you don’t know how many numbers there will be. You could use an access type to create a linked list, where each item in the list points to the next item. This way, you can add as many items to the list as you want, without having to know the size of the list beforehand.

Access types are very useful for modeling potentially large structures, like memories or FIFOs, but they are not supported by synthesis tools.

The 1987 version of VHDL saw the introduction of access.
 * Notes

Not synthesizable

See https://peterfab.com/ref/vhdl/vhdl_renerta/source/vhd00001.htm


 * Syntax

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after
- The VHDL command “after” is used to introduce a delay in the assignment of a signal. It is used to specify the time after which the signal should be assigned a new value. For example,  means that the signal x will be assigned the value '1' after 10 nanoseconds have passed.
 * Introduction

The 1987 version of VHDL saw the introduction of after.
 * Notes

Not Synthesisable.

Delays are not supported in functions.

It is important to note that the “after” command has to do with the delay model. In the default VHDL inertial delay, your second “slower” signal assignment statement cancels the future update of the first. You could schedule multiple updates in one statement to correct this, for example:.

see http://gmvhdl.com/delay.htm


 * Syntax

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alias
-
 * Introduction

Aliases, are alternative names for existing objects, such as signals, variables, constants, types, etc. Aliases can be useful for making your code more readable, avoiding name conflicts, or accessing parts of an array or a record.

You can also use a special syntax << ... >> to create external names, which are aliases that can access objects in other design units or hierarchy levels

The 1987 version of VHDL saw the introduction of alias.
 * Notes

Aliases are local to the declarative region where they are defined, and they cannot be redefined or overridden.

Aliases cannot be used as targets of assignments.

Aliases can be used in any place where the original name can be used, such as expressions, statements, or subprogram calls.

See https://peterfab.com/ref/vhdl/vhdl_renerta/mobile/source/vhd00003.htm


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all
-
 * Introduction

The keyword "all" in a context declaration is a way to specify a set of libraries, packages, and entities that are used in a design unit.

For example, you can write:

This means that all the design units that reference this context will have access to the ieee library and the packages std_logic_1164 and numeric_std. The keyword "all" in this case means that all the design units in the current working library can use this context.

Since VHDL-2008, the keyword "all" is used to indicate that the sensitivity list of a process should be inferred by the tool, rather than explicitly specified by the designer.
 * Alternative

The sensitivity list is a list of signals that trigger the execution of the process when they change their values.

For example, consider the following process that implements a D flip-flop with asynchronous reset:

The sensitivity list of this process is (i_clk, i_rst), which means that the process will run whenever i_clk or i_rst changes. However, we can also use the keyword "all" to let the tool infer the sensitivity list for us:

This is equivalent to the previous process, as the tool will automatically determine that i_clk and i_rst are the only signals that affect the behavior of the process.

Using the keyword "all" can be convenient and less error-prone, as it avoids the need to manually update the sensitivity list when adding or removing signals from the process.

Some tools may not support this feature, or may generate different results depending on the sensitivity list inference algorithm so check the tool documentation and verify the synthesis and simulation results before using the keyword "all" in a clocked process.

The 1987 version of VHDL saw the introduction of all.
 * Notes



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and
-
 * Introduction

This keyword is used to represent the logical AND operation, which is a basic building block in digital logic circuits.

The `AND` operator performs a bitwise AND operation if the operands are vectors (arrays of bits like std_logic_vector) or performs a logical AND operation if the operands are of type bit or boolean.

If all inputs are ‘1’, the result is ‘1’. Otherwise, the result is ‘0’.

This behavior mimics the functionality of an AND gate in digital electronics.

The 1987 version of VHDL saw the introduction of and.
 * Notes

see

https://fpgatutorial.com/vhdl-logical-operators-and-signal-assignments-for-combinatorial-logic/
 * Syntax

In this example, signal  will be ‘1’ if both   and   are ‘1’. Otherwise,  will be ‘0’.

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architecture
-
 * Introduction

The term "Architecture" assumes a pivotal role. It serves as a formal blueprint associated with an entity declaration, tasked with elucidating the internal organization and operation of a design entity. In essence, an architecture delineates the behavior, data flow, or structural composition of the design entity with precision and rigor. This technical construct finds utility in describing the intricate relationships between input and output ports within a design, encompassing two primary components: declarations and concurrent statements. Declarations encompass various elements, including types, signals, constants, subprograms, components, and groups, while concurrent statements articulate how inputs interact with outputs, with diverse statement types allowing for flexibility in expressing design functionality. Architecture, in the context of VHDL, embodies a systematic and unambiguous approach to defining the fundamental characteristics of digital systems, laying the foundation for their subsequent implementation and analysis.

The architecture is used to detail the behavior, data flow, or structure of a design entity.

An architecture linked to an entity primarily delineates the inner relationships between the input and output ports of the entity. It consists of two primary components: declarations and concurrent statements.

The declarative part of an architecture encompasses various types of declarations, such as types, signals, constants, subprograms (functions and procedures), components, and groups. Detailed information on each of these can be found in their respective topics.

Concurrent statements, on the other hand, describe how inputs relate to outputs within the architecture. These relationships can be expressed through diverse types of statements, including concurrent signal assignments, process statements, component instantiations, concurrent procedure calls, generate statements, concurrent assertion statements, and block statements. These statements can be written in various styles, such as structural, dataflow, behavioral (functional), or mixed, depending on the intended design.

Structural descriptions rely on component instantiation and generate statements, enabling the creation of hierarchical projects that range from simple gates to intricate components, encompassing entire subsystems. These components connect through ports, as illustrated in Example 1 for a BCD decoder.

Dataflow descriptions employ concurrent signal assignment statements. Each statement can activate when any of its input signals change, describing the circuit's behavior and structure, as showcased in Example 2.

In contrast, a behavioral description, as demonstrated in Example 3, includes only one or more processes, each containing sequential statements. This approach focuses solely on the expected functionality of the circuit, without specifying hardware implementation details.

A mixed architecture description, as seen in Example 4, combines both behavioral and structural elements within the same architecture body. The 1987 version of VHDL saw the introduction of architecture.
 * Notes

An entity can have multiple architectures, but an architecture cannot be assigned to different entities.

An architecture must be associated with an entity.

All declarations within an entity are entirely visible and accessible within any architecture assigned to that entity.

Different types of statements, such as processes, blocks, concurrent signal assignments, component instantiations, etc., can coexist within the same architecture.


 * Syntax

Example 1:

Example 2:

Example 3:

Example 4:

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array
- Introduction to the Keyword "Array" in VHDL:
 * Introduction

In VHDL, the keyword "Array" is a versatile data type that plays a pivotal role in structuring and organising data. In VHDL, an array is formally defined as a type whose value consists of elements of the same subtype, making it ideal for managing homogeneous data sets. What distinguishes each element within an array is an index (or indices, for multidimensional arrays) associated with it. These indices are required to be values of a discrete type and must fall within the specified index range.

In simpler terms, an array is like a container that holds elements of a consistent type, and each element is uniquely identified by its index. The number of indices directly corresponds to the number of dimensions; for example, a one-dimensional array has one index, while a two-dimensional array has two.

Arrays in VHDL come in two flavors: constrained and unconstrained. A constrained array has a fixed size, determined either by a discrete type mark or a specified range. In contrast, an unconstrained array does not have a predefined size; its size is only determined when you declare an object of that type.

For instance, VHDL's Package STANDARD includes predefined unconstrained array types like STRING and BIT_VECTOR. These arrays are widely used, with STRING elements indexed by positive values and BIT_VECTOR elements indexed by natural values.

Arrays in VHDL can be manipulated using various techniques such as indexing, concatenation, aggregates, and slices. These methods provide flexibility in accessing and assigning values to array elements, making them a crucial component of VHDL programming.

It's worth noting that while arrays are a powerful tool in VHDL, not all synthesis tools support multidimensional arrays. There are exceptions, such as two-dimensional "vectors of vectors," and some synthesis tools allow limited support for two-dimensional arrays.

In summary, arrays in VHDL are fundamental data structures that allow you to efficiently manage and manipulate collections of data, making them a key element in VHDL programming.

The 1987 version of VHDL saw the introduction of array.
 * Notes
 * Syntax

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assert
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 * Introduction

The 1987 version of VHDL saw the introduction of assert.
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attribute
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 * Introduction

The 1987 version of VHDL saw the introduction of attribute.
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begin
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 * Introduction

The 1987 version of VHDL saw the introduction of begin.
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block
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 * Introduction

The 1987 version of VHDL saw the introduction of block.
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body
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 * Introduction

The 1987 version of VHDL saw the introduction of body.
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buffer
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The 1987 version of VHDL saw the introduction of buffer.
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bus
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The 1987 version of VHDL saw the introduction of bus.
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case
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The 1987 version of VHDL saw the introduction of case.
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component
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The 1987 version of VHDL saw the introduction of component.
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configuration
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 * Introduction

The 1987 version of VHDL saw the introduction of configuration.
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constant
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 * Introduction

The 1987 version of VHDL saw the introduction of constant.
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disconnect
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 * Introduction

The 1987 version of VHDL saw the introduction of disconnect.
 * Notes
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downto
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 * Introduction

The 1987 version of VHDL saw the introduction of downto.
 * Notes
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else
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 * Introduction

The 1987 version of VHDL saw the introduction of else.
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elsif
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 * Introduction

The 1987 version of VHDL saw the introduction of elsif.
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end
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 * Introduction

The 1987 version of VHDL saw the introduction of end.
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entity
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 * Introduction

The 1987 version of VHDL saw the introduction of entity.
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exit
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 * Introduction

The 1987 version of VHDL saw the introduction of exit.
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file
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 * Introduction

The 1987 version of VHDL saw the introduction of file.
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for
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 * Introduction

The 1987 version of VHDL saw the introduction of for.
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function
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 * Introduction

The 1987 version of VHDL saw the introduction of function.
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generate
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 * Introduction

The 1987 version of VHDL saw the introduction of generate.
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generic
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 * Introduction

The 1987 version of VHDL saw the introduction of generic.
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guarded
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 * Introduction

The 1987 version of VHDL saw the introduction of guarded.
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if
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 * Introduction

The 1987 version of VHDL saw the introduction of if.
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in
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 * Introduction

The 1987 version of VHDL saw the introduction of in.
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inout
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 * Introduction

The 1987 version of VHDL saw the introduction of inout.
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is
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 * Introduction

The 1987 version of VHDL saw the introduction of is.
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label
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 * Introduction

The 1987 version of VHDL saw the introduction of label.
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library
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 * Introduction

The 1987 version of VHDL saw the introduction of library.
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linkage
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 * Introduction

The 1987 version of VHDL saw the introduction of linkage.
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loop
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 * Introduction

The 1987 version of VHDL saw the introduction of loop.
 * Notes
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map
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 * Introduction

The 1987 version of VHDL saw the introduction of map.
 * Notes
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mod
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 * Introduction

The 1987 version of VHDL saw the introduction of mod.
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nand
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 * Introduction

The 1987 version of VHDL saw the introduction of nand.
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new
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 * Introduction

The 1987 version of VHDL saw the introduction of new.
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next
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 * Introduction

The 1987 version of VHDL saw the introduction of next.
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nor
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 * Introduction

The 1987 version of VHDL saw the introduction of nor.
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not
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 * Introduction

The 1987 version of VHDL saw the introduction of not.
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null
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 * Introduction

The 1987 version of VHDL saw the introduction of null.
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of
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 * Introduction

The 1987 version of VHDL saw the introduction of of.
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on
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 * Introduction

The 1987 version of VHDL saw the introduction of on.
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open
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 * Introduction

The 1987 version of VHDL saw the introduction of open.
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or
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 * Introduction

The 1987 version of VHDL saw the introduction of or.
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others
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 * Introduction

The 1987 version of VHDL saw the introduction of others.
 * Notes
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out
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 * Introduction

The 1987 version of VHDL saw the introduction of out.
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package
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 * Introduction

The 1987 version of VHDL saw the introduction of package.
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port
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 * Introduction

The 1987 version of VHDL saw the introduction of port.
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procedure
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 * Introduction

The 1987 version of VHDL saw the introduction of procedure.
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process
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 * Introduction

The 1987 version of VHDL saw the introduction of process.
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range
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 * Introduction

The 1987 version of VHDL saw the introduction of range.
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record
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 * Introduction

The 1987 version of VHDL saw the introduction of record.
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register
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 * Introduction

The 1987 version of VHDL saw the introduction of register.
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rem
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 * Introduction

The 1987 version of VHDL saw the introduction of rem.
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report
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 * Introduction

The 1987 version of VHDL saw the introduction of report.
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return
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 * Introduction

The 1987 version of VHDL saw the introduction of return.
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select
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 * Introduction

The 1987 version of VHDL saw the introduction of select.
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severity
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 * Introduction

The 1987 version of VHDL saw the introduction of severity.
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signal
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 * Introduction

The 1987 version of VHDL saw the introduction of signal.
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subtype
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 * Introduction

The 1987 version of VHDL saw the introduction of subtype.
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then
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 * Introduction

The 1987 version of VHDL saw the introduction of then.
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to
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 * Introduction

The 1987 version of VHDL saw the introduction of to.
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transport
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 * Introduction

The 1987 version of VHDL saw the introduction of transport.
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type
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 * Introduction

The 1987 version of VHDL saw the introduction of type.
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units
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 * Introduction

The 1987 version of VHDL saw the introduction of units.
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until
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 * Introduction

The 1987 version of VHDL saw the introduction of until.
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use
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 * Introduction

The 1987 version of VHDL saw the introduction of use.
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variable
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 * Introduction

The 1987 version of VHDL saw the introduction of variable.
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wait
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 * Introduction

The 1987 version of VHDL saw the introduction of wait.
 * Notes
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when
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 * Introduction

The 1987 version of VHDL saw the introduction of when.
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while
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 * Introduction

The 1987 version of VHDL saw the introduction of while.
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with
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 * Introduction

The 1987 version of VHDL saw the introduction of with.
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xor
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 * Introduction

The 1987 version of VHDL saw the introduction of xor.
 * Notes