Oscilloscope Design

=Preface= This book is about how an oscilloscope might be designed. I am aiming at the use of an ordinary TV for display but my design can actually be used by a PC also because data can be parallel read. I will describe all the parts needed for an oscilloscope. Actually I have designed a version of this some 30 years ago, it was my exam work which I am showing. This new version does however not use four wire-wrapped circuit boards for all the logic gates, instead it uses a Spartan FPGA.

=TV-Scope Block Diagram=

This picture shows a block diagram of our TV-Scope. It consists of five modules. The first module is an input interface (KOI) which takes care of the signals from three rotational encoders used to set the different two channel attenuations (Vots/DIV) and sweep-time values (Sweep-time/DIV). The second module (KOA) is the analog heart of our TV-Scope while it is an amplifier of high bandwidth. The third module is the trigger module (KOT) which makes you trig on a chosen signal level and slope. The fourth module (KOL) is the digital heart of our TV-Scope. The fifth module is only an interface for TV (KOV).

KOF, Oscilloscope Front
Here you see my mechanical structure. Each unit has its own circuit board. As you can see it doesn't fit perfectly to the block diagram above but here it is more practical. If you want to sell a unit, this is more appropriate meaning that the different units are isolated from each other and kind of stands alone. Personly I think that the KOA has the highest commersial potential, next comes the KOT and perhaps even KOR is useful for others. KOL and KOV are however so specialized that noone would want or need them.

I have upgraded this picture somewhat, the Auto/Norm triggering feature in KOT has been eliminated while it is now hardwired in KOL (see the new version of Ts_Enable).

Critical Components
The mechanical parts (bold faced) in this list are referred to the KOF above. The electrical parts are referred to the rest of our TV Scope. All parts are rather critical. The SRAMs are critical with regard to access time (12ns). The PROMs are not critical other than memory space. The PROMs can be changed to whatever and need mainly to be of correct size. I have chosen 27C512 partly because I like that (E)PROM, partly because I can program them with my Dataman S4 programmer. While the speed of it all is important I have also chosen a fast OP-amp (LM318). The comparator (CMP01) is obsolete but I bought a couple from ebay a while ago and kind of like it (while I also used it in my original TV-Scope). The two special ICs regarding composite TV-sync generation and extraction are not necessary because Spartan can emulate them but I used them in my original TV Scope and they minimizes the design work of the Spartan.

KOR, Oscilloscope Regulators
At input the regulators see some 17Vp. AVss need not 3m3 of buffer capacitance while the current drawn there is rather low but I like symmetry. AVcc does not draw so much current either but all the other regulators will so here we need a rather high capacitance. To look at the different currents we can supply we must first check what the voltages are over the different regulators. For Vcc we have 12V, for Vdd we have 14V, for Vaux we have 15V and for Vint we have same 16V.

All regulators can supply around 1,5A but using no cooler a TO220 can't handle more than some 2W. For say Vint this means a maximum current of 2/16=125mA which isn't that much. I have no idea how much my Spartan will draw at 40MHz but I imagine not so small a current. The Spartan has three supplies (3,3/2,5/1,2V), which one draws current? Or do they all do?

I think 1,2V is the core supply and I recon it is here it draws current and 125mA doesn't sound enough. My plan is to put a cooler on all Spartan supplies. This cooler will be a push-on cooler with a K of some 16K/W and for what I have learned the maximum allowable power dissipation is then

$$P=\frac{125K}{K+K_{iso}+K_{jc}}$$

where K is the cooling factor of the cooler, Kiso is the thermal resistance of the isolation and Kjc is the thermal resistance of the junction to case. Using Kiso=0,3, Kjc(TO220)=2 and K=16 we get 7W. Now Vint can draw 7/16=0,44A and while all other regulators has less differential voltages over them they can deliver more. Let's say that they deliver some 0,5A maximum, are the buffer capacitors large enough? As you know a good approximation for the voltage drop from a capacitor input filter is

$$\Delta V=\frac{I}{C}\Delta t$$

so for a time delay of 10ms using 50Hz mains, full wave rectification and 6,6mF we have 0,8V peak to peak rippel. If AVcc/AVss (12V) is made to function at all times the voltage drop can't be more than 17V-(12V+3V)=2V while the regulators need some 3V over them to regulate, so the overall margin isn't that high. In other words, the total current to supply the system can't be much more than some 1A.

On the other hand I plan to use an AC-adaptor being able to supply 1,7Aac which means some 1,2Adc maximum.

KOI, Oscilloscope Interface
This is a theoretical unit while I am a bit uncertain how to design it so I design for all rotational encoders and the attenuator circuit here. The two different rotational encoder solutions will be merged into KOA and KOL at a later stage. I am aiming at a two channel oscilloscope so there will be two 12-step rotational encoders (in KOA) and one 18-step rotational encoder (in KOL). The POR-circuit displayed will reside in all of these three modules making three separate POR-circuits.

Tsw and POR Control
Here I show a drawing of a /POR circuit which goes low at the moment the supply voltage is put on. It holds its low level for a short time (~100ms) which enables all ICs being set to a known start value. I also show a circuit that generates five output datas (read addresses) from a rotational encoder, these addresses are then used to set the different Tsw/DIV sweep-times. The use of a rotational encoder is rather obligatory nowadays because multiple pole and throw rotational switches are obsolete and if they may at all be found they cost too much. The other circuit I am showing simply sniffs the address and shows what the setting is by simple LEDs (or LED Arrays in my case). I have an analogue oscilloscope bought from China that I like but I really dislike the feature that when you are out of range it beeps. Here I instead use the feature that when you turn the knob clockwise more than to the shortest Tsw (625ns) it switches to the longest Tsw (0,5s) but if you turn the knob counter clock wise more than to the longest Tsw, it stays there.

My thought around this is kind of advanced because when I now also wish to use this feature for the Volts/DIV this means that you will go from 1mV to 5V if you overturn the knob clock wise (CW) but you will stay at the 5V range anti clock wise. Imagine having a signal of some 50V and you happen to turn the knob counter clock wise (CCW) at the 5V range. Would you like the input amplifier to be exposed to 50V?

The input amplifier (KOA) is set for a 1mV sensitivity which is attenuated down by the attenuator for the different Volts/DIV, a sudden 50V here may not be so good. I seem to have designed so that the input can be some 22V without destroying the input protection diodes. A normal oscilloscope limit here is some 300Vp.

Attenuator Control
Here I use a single HC191 counter for the chosen attenuator voltage levels (12 levels). I then decode the 4-bit address and use a priority encoder to lit a LED for each level. The HC191 will reside in KOA and not in the Spartan (or KOL) while this gives the overall design a more pedagogic feature due to separate PCBs for KOA and KOL.

The OOR-feature (Out Of Range) is the same as above but here we move from 1mV to 5V (0h address) while turning the knob CW, turning the knob CCW at 5V however means that we stop at 5V.

The Attenuator
The reed relays draw more than 25mA which is more than HC-MOS can supply so we need some kind of buffer, I use ULN2003. The output from the attenuator control above is then inverted so we need to invert these before driving ULN. While Cin is not zero and we wish the attenuation to be frequency independent we need to have a capacitor over both attenuating resistors. At 1mV/DIV the signal is straight into KOA so here we only see Cin but due to standard probes expecting 25pF we must add some 17pF. 1mV/DIV is thus a special case but we may see it as at any attenuation level, the probe must see 25pF.

There are four governing formulas to consider:

$$R2C2=R3'C3'...[1]$$

where

$$R3'=R3//Rin$$

$$C3'=C3+Cin$$

while we need to consider KOA input, then we have

$$1/Att=\frac{R2}{R3'}+1 ...[2]$$

$$R2+R3'=1M ...[3]$$

which is the expected probe resistance and finally

$$\frac{1}{C2}+\frac{1}{C3'}=\frac{1}{25pF} ...[4]$$

where 25pF is the expected probe capacitance.

This simplifies to

$$C2=25(1+\frac{1}{1/Att-1})...[A]$$

$$C3'=(1/Att-1)C2...[B]$$

$$R3'=\frac{1M}{1/Att-1}...[C]$$

$$R2=R3'(1/Att-1)...[D]$$

Here we only need to consider the special cases above regarding the physical R3/C3 components. Att is by the way always less than one because it is a simple voltage divider and I think the formulas becomes more smooth if we use 1/Att.

Attenuator Table
Here I have calculated all attenuator values for our 12 different settings. I have aimed at a tolerance of around 2% when it comes to both frequency and level. While this tolerance is rather narrow I partly need to parallel capacitors partly use special 1% resistors of the E96 series. The tolerance for the capacitors is normally rather bad (don't hope for more than 10%) so this part of the attenuator table isn't that precise. For the high sensitive levels (low attenuation) the capacitance of the input stage (KOA) has to be considered. I reason that the input capacitance of KOA will be less than 8pF while the input protection diodes (1N4148) are said to have a maximum capacitance of 8pF and while this value is measured at a reverse voltage of zero volts, the actual capacitance when they are biased -12V will be better. The input capacitance of the KOA without the diodes is estimated to be 0pF mainly because the output capacitance of the current generator is rather low while it comes in series with the very low input capacitance of the transistors.

It suddenly strikes me that our KOA input resistor (limiting the protection diodes current) has a capacitance of around 0,1pF which is much smaller than our 25pF and also comes in series with the net diode capacitance of around 8pF. So for practical purposes we may neglect KOA input capacitance. I have now done that and corrected the attenuator table accordingly.

My choice of input resistor is 470Ohms, this while my two analog oscilloscopes has 250Vp maximum marked at the channel inputs and 470Ohm will approximatelly limit the current of input protection diodes to 250V/470Ohm=0,5A while 1N4148 can withstand 0,5A as repetitive peak current (0,3A max DC). In real life there will not be a steady DC voltage of 250V applied to the inputs (at worst case) but just a peak voltage so my limitation suffices.

Another reason for limiting the input voltage to 250V is that this is a standard voltage rating for capacitors. However, the different capacitors sees different voltages, if we look at R2 this one sees almost all at the 5V setting and none at 1mV setting so to speak but I think it is a good method if all capacitors can withstand 250V. The only problem is that my stock of capacitors are not all 250V so I plan to buy them all in a special customized order (I don't need so many as you may appreciate).

KOA, Oscilloscope Amplifier
At the differential input stage (A) I use a pair of BF245A JFET transistors. This is manly because I want to be able to set the input resistance high, if you do that with bipolar transistors you would need Darlingtons to limit the input bias current and thus the offset (due to the other transistor working with lower resistors) and I don't like that. Here I also use a current generator (T3) mainly for ease of setting the bias current while it also generates lots of CMRR. The next stage (B) is a C-stage input capacitance driver while high drive impedance results in a low bandwidth. The collector resistances R3/R4 aren't that large but their resistances are much larger than the output resistance of an emitter follower. At the C-stage I use a pair of Germanium High Frequency Transistors (AF239) and I do this mainly for fun. This is the gain stage and I use differential connection of the transistors up to here because the DM gain is higher than the CM gain. You could decouple a single ended gain transistor emitter resistor to get the same gain but I don't like that, I think it is smoother to keep the signal differential. At stage (D) there is just an emitter follower to enable low output impedance. Some of this low impedance is however ruined by the output connection where I have set the Variable pot to 1k along with a 470Ohm resistor. A sloppy estimation of the maximum output impedance is 250Ohm, for a single pole you would want the pole (fp) to lay 3 times higher in frequency for -0,5dB so if we wish to measure 10MHz without problems, the pole should lay at 30MHz. Our sloppy estimation of 250Ohms then tells us that the maximum capacitance of the next stage should be 21pF.

I will now describe the different stages, beginning with the input stage (A). While CM gain is rediculously low I omitt that and move on to DM gain, the DM gain is

$$Av_{DM}/2=\frac{\mu Rd}{rp+Rd}=\frac{375 \cdot 2k2}{125k+2k2}=6$$

This is a rather low gain but we use rather small drain resistors compared to the "plate resistance" (rp). At the next stage the voltage gain is almost exactly 1 due to emitter followers and I will not show that. At the C stage we then have our serius gain, the gain expression for these bipolar transistors is

$$Av_{DM}/2=\frac{\beta Rc}{Rs+hie+Rc}=\frac{40\cdot 2k2}{25/3,9+500+2k2}=32$$

Here the output resistance for stage B (Rs) is estimated to 25/Ic while gm is said to be Ic[mA]/25 for small signal transistors. In the datasheet for the AF239 I find that g11 is 2mS at 800MHz and 45mS at 200MHz, while this is an admittance hie may be evaluated as being 500Ohms as worst.

So the total gain is some 6*32=192. This is however less than I need, I need 215. Interesting! At my position R3/R4 may be increased rather much, one thing then is that bias current will have to be lessened another thing is that stage B has input capacitance which isn't that critical but will worsen bandwidth while I am aiming at at a GBW of 2,15GHz. On the other hand I have used the worst g11 in my calculations.

Building this "OP-amp" is very exciting, will I hit more than 215 in gain and more than 2,15GHz in bandwidth?

KOT, Oscilloscope Trigger
This unit selects four different kind of trigger sources and enables a trigger pulse to start the sampling at the wanted point. The sources are CH1, CH2, EXT and LINE where the channel inputs comes directly from KOA, EXT comes from an external trigger source and LINE comes from the 50Hz AC Line. There is a Probe Cal gadget that makes it possible to trim probes. There is also a rotational switch (V-Mode) that selects what to send to the ADCs. After IC10:b there is however a misunderstanding which I am correcting below.

New Version
Auto triggering will be enabled in KOL so the Ready signal is not needed. Auto triggering will always be enabled so that DC-signals can be displayed. Up to now a display of a DC signal has required the trigger source being set to LINE while the KOT only gives triggering signal for AC signals. I will explain further at the Ts_Enable unit.

KOL, Oscilloscope Logic module
All digital circuits except for SRAMs, PROMs, Sync-ICs, monostable multivibrators and hazard generators will be implemented in the Spartan FPGA. I think that SRAMs, monostable multivibrators and hazard generators are impossible to implement, I do however think that ROM functions are possible to implement but do not want to mix Gate CAD (ECS) with VHDL/Verilog while I also suck at programming. The Sync-ICs can be implemented in the Spartan but I think there will be less programming work if I use available ICs instead.

Ts_Enable
This unit sniffs the input trigger and is, with the use of a monostable multivibrator, set high when there has come a trigger signal from the analog part of our TV Scope. The time the multivibrator is set is slightly longer than it takes to sweep the scope with the use of maximum sweep time (10*Tsw_max) while there are 10 "squares" in the x direction, each Tsw.

This unit will have to reside outside of the Spartan.

New Version
This version incorporates an auto trigger which makes DC-signals being displayed. It works in such a way that the Spartan simulates a whole 10Tsw (or screen width) delay and if no samples has come before 10Tsw an auto trig is generated. A new sharp trigger signal then has <10Tsw before auto trig which means that the sitting AC-signal will take over if its trigger comes before the auto trigger which is the normal case for a screen width because we are viewing a signal that perhaps varies within one Tsw only.

Ts/Tswap Generator
Here we divide a 40MHz crystal to give the different sweep-times. Actually the sweep-times (Tsw) themselves are not generated but Tsw/50 which gives the sampling time (Ts). A signal called Tswap (40MHz) is also created which is used to move the sampled data from the Sampling Memory to the Read Memory while the samples can not be moved other than during the time for the vertical sync and it is a good thing to move the samples with highest possible speed.

Except for the PROM, the component type numbers are not relevant because this unit will reside in the Spartan.

[I will remove this later on and just update the picture. As a note I have come to the conclusion that showing the grid on a TV screen using 500 samples means that I need a PROM of 128kB, moving down to 250 samples only requires half which means that I can use my precious 27C512-10 for both the Tsw division and the grid. This then has the advantage that the rest will be more simple when it comes to design (due to only one full byte of counters) and by halving the number of samples per division (Tsw) I can move lower when it comes to Tsw and thus view signals of higher frequency. The drawback is that I will have to redesign this picture and also the programming table below, another drawback is the resolution i.e 25 samples (instead of 50) per Tsw].

New Version
Below I have reduced the number of samples per Tsw from 50 to 25. This is because I want to use my precious 27C512 which are only 64kx8 while I originally needed 128kx8. 25 samples per Tsw does however mean that I can measure higher up in frequency while the resolution then thus is somewhat worse but I think that 25 samples per Tsw (division) is enough. The super fast SRAMs are the limitation.

PROM Programming Table
The 40MHz crystal is here divided to give us the Ts and Tsw we need (where Tsw is the sweep-time per divison and the number of divisions x-wise in an oscilloscope is ten, each Tsw is here sampled 50 times). As you can see the shortest Ts is the crystal period and I think that the SRAMs need to have half of this time as access time because I have had some problems with 20ns memories.

New Version
Here I have upgraded the programming table for the Tsw PROM. I have not done so much studies but only changed the above original programming table to this one. I may however have to check it but that is an easy thing.

Sampling/Swap Mode Switch
This unit switches between sampling (Ts) and swap (Tswap). At sampling the Sampling-memory is filled with data and there is a LAR (Last Address Ready) when the last address has been "sampled". This first LAR switches to swap but swap can not be done other than during vertical sync (here named swap-start), also the total sampling time may exceed 20ms (half TV page time) so we have to wait until sampling has finished before we can swap. At swap-start the content of the Sampling-memory is copied to the Read-memory with a high speed (40MHz in this case) and while the speed is so high the copying will finish before the vertical part of the TV picture has finished. When all data has been swaped there is another LAR which via NTE enables a new trigger.

At the chosen start-line, the samples will be displayed. There is also an area of the TV-screen that is enabled only for our 256 ADC data range (En.D-lines) where this signal also makes it possible to adjust the displayed data horizontally (X-Pos).

New Version
Here I change the "Swap Start" to the verikal pulse (VO) instead while the VO is of short duration (around 200us) and hazards are not allowed inside the Spartan. By doing this I may also be able to skip the sync separating IC (LM1881) and only use the sync generator IC (MSM5258) which have the signals I need.

Ts/Tswap Address
Here we generate addresses for Ts and Tswap. The counters are initiated to Fh while the first clock-pulse sets them to our first sample of address 0h and from there the counters are just stepped up. We also generate a signal LAR (Last Address Ready) which tells us that the maximum address has been reached (i.e all of our 500 samples has been stored). The LAR is generated twice, firstly after sampling and secondly after swapping and it is only when swap is finished the LAR generates a NTE (New Trig Enable) so that there can be a new sampling.

While the used counters has syncronous load the clock needs to be delayed a short time (done by a small capacitor, C1) because /LD has to be low when the clock comes. I will change the counters to asyncrous ones instead.

New Version
Here I eliminate one counter to reduce the number of samples from 500 to 250. This has to do with my precious 27C512 EPROM while it also simplifies a lot.

In this drawing I use the HC193 instead of the HC163. This is just schematic while the counters will reside inside the Spartan. I am however aiming at a counter in the Spartan library that has asynchronous Load. In the former version I used a counter that had synchronous load which complicate things (the load pulse was had to be delayed for the clock). The benefit with the former counter is that it is faster but as I readily have told you, this doesn't matter (due to Spartan being fast).

I relay an inverted version of the Ts/Tswap clock (and has called it /Ck) and this is rather important because it gives a delay of the whole clock when writing to the memory. The memory can't be written at the same time the address is generated.

The LAR-signal is looked to overshoot (250 samples means 0-249) but what happens is that when the sample number is 249 the asynchronous load loads FFh so that when the first Ts/Tswap comes we have the address 0.

The LAR pulse is short, it is only a spike of around tpd duration. We do however not need a full pulse here, tpd is enough to initialize the counters. This way we have a rather exact time delay of 250 Ts/Tswap.

TV_Read (adr+sim.data)
Here we generate read addresses for reading by the Sync-IC. It starts with the vertical output pulse (VO) which goes high at the odd field and the address is stepped forward by the D-Read signal. The signal En.D-Lines tells the system where to start reading and displaying the data on the TV screen. En.D-lines sets where on the screen we want the data to be displayed. Sim.Data is a simulated data bus which is used to be compared with the (inverted) ADC data. The data from the ADC is inverted (either analoglly or digitally) because the first line on the top of the TV screen has the line number 0 while the line numbers are increased downwards so to be able to compare the line-data with the ADC data the ADC has to be inverted.

New Version
Here I also eliminate a counter to handle 250 samples instead. When D-lines is not enabled and the vertical pulse (VO) comes the simulated data (Sim.Data) and the Read-address will be set to FFh. At each line-read (D-Read) the simulated data will be stepped up at the same time the Read-Address is stepped up. So at first D-read pulse the simulated data is zero and the address is zero. Simulated data begins from the top of the TV screen so the A/D value will have to be inverted to match the line number (simulated data). When the simulated data equals the inverted A/D value, the pixel is lit.

This version is more simple than the original partly because I here use up/down counters that have asynchronous Load and Clear partly because the number of addresses/samples is two nibbles long only.

In practice this doesn't matter because I plan to use predefined counters in the Spartan library but right now I do not know what they are, on the other hand I can manufacture counters by using gates only, which I have done for my CPU, and that I know resides in the library.

Memory Handling
The sampling is done to the Sampling Memory. When a sampling is done and the vertical pulse has come, the sampled samples are moved by the swap-clock to the the Read Memory. After this is done the Read Memory is read. This is because the samples can only be read while the TV is showing the samples and we need to see the samples all the time.

Grid PROM
The pixels are lit when the simulated data equals the programmed data. The simulated data is linearly increased from the top of the screen where the first line has the value 0, inverting the data makes the data have the value 0 too. So when the line number is the same as the data the pixel is lit. The programming of the Grid PROM is however not so simple.

New Version
Here I reduce the number of samples to be able to use my precious 27C512 instead. This means that the resolution per Tsw (division) will go from 50 samples per division to 25 samples per division. It however also makes me being able to measure higher frequencies. Consider 50Ts/Tsw and the shortest Ts is 25ns, then one hole division will take 25ns*50=1,25us. Now an estimation of the shortest period of a signal to be visualized is some 1,25us/5=250ns. The inversion of this makes the highest possible frequency to be seen 4MHz. Halving the resolution will instead enable the visualization of 8HHz.

I do not plan to implement the standard feature of analog oscilloscopes that is a 10X Mag so we are stuck with only being able to measure frequencies around 8MHz maximum.

The programing of this Grid PROM is however not that trivial. At the original situation some 30 years ago it took the fastest available computer at Chalmers some two hours!

Video Out Generator
This drawing is preliminary but rather important because it fundamentally determines how to read the sampling memory. My plan is another than this original version where we have an output signal called "Swap-start". I used two SRAMs at this occasion but is now contemplating the use of only one SRAM per channel while the MSM5258 PAL Sync Generator actually has a reset which may perhaps be used to start the reading of the sampled SRAM at a controlled screen position. The original solution did have to wait for the vertical sync.

New Version
Here I eliminate the sync separator IC (LM1881) to use the sync generator IC only (MSM5258) instead. The vertical output pulse (VO) is of around 200us in length and it is a pulse that goes positive at odd fields. I anticipated a problem here because if we use shortest Tsw one 10Tsw sweep (a full screen) will take 250*25ns=6,25us which also is the same as the swap-speed. So the obligatory sampling+swap will take 12,5us that is, if it takes a longer time than the sampling time which means that the swapping will have to wait for the next vertical pulse (VO). But this is always the case if we consider long Tsw where 10Tsw can take up to 5s (10*0,5s/DIV). Here we wish to see something on the screen in spite of the sampling not being ready. So this is not a problem.

A problem could be the fact that I don't sniff the actual flank of the VO but is aiming at using the 200us VO pulse instead (while the Spartan can't handle hazards) which means that if 10Tsw is less than 200us we have to wait for the next VO. On the other hand, if 10Tsw is longer than VO we have to wait for VO anyway.

I have come to the conclusion that the outputs of the sync-generator IC are open drain. This way it is easy to adapt the output voltage to the Spartan. The values of the resistors are kind of irrelevant but I will use 10k.

Line Field Decoder
This module generates a signal that is high during all 256 lines (which is our data range). I have a hard time understanding it and will try to understand it better. It is copied as an application example for the LM1881 sync separator.

I think I now understand it better and have made some corrections, the most brutal correction is the elimination of the inverter from the borrow output of Nr of Continues Lines while this is a negative going pulse when all continues lines have been counted. At that stage the latch have to be reset so that the final counting of the continues lines enables a one at the count down (CD) input to stop the counting. The continues lines is the last that happens, then a odd/even screen is generated.

Here I however though that while there are capacitors involved here I need to place this part outside of the Spartan. Now I however think that this isn't necessary because both the Composite Sync (CS) and the Vertical Pulse (VO) are indeed pulses. The exact start of the lines will however probably have to be adjusted in retrospect.

I reason like this, while they are pulses it doesn't really matter when they are in control because they will come in synchronization anyway. If the triggering of the internal counters with regard to CS is delayed 14us pulse or not doesn't matter much, likewise if the triggering by the VO pulse is delayed 200us.

TV-Read Clock
This unit gives offset possibilities for where we horizontally wish to show our samples. It also gives independent offset possibilities for both the Grid and Data. Due to this we may horizontally adjust the grid to the center of the TV screen along with X-POS adjustment of our data. X-POS is rather important because we often wish to adjust so that the signal crosses the grid at a certain place so that we more easily can estimate its frequency.

External Read
Here we try to read the sampled data externally. This is preliminary done by creating two signals (VO and D-read) in a PC. VO is a positive pulse of short duration (normally ~200us) and D-Read is a synthesized horizontal pulse that reads the data in syncronization with the read addresses. This syncronization is enabled internally so to read data without PAL syncronisation we need to take care. When there has come a NTE (sampling and swap is finished) it means that fresh data resides inside the Read memory but reading of the Read memory may take a shorter time (compared to 10Tsw) than before next NTE (e.g a new sampling and swap), in that case we just wait for NTE and sends VO until NTE comes, that is we read one time and send VO until NTE goes high then we read again (new data).

KOS, Oscilloscope Spartan
This is not a separate unit while it is incorporated in KOL. I do however need to specify several steps (and Gate-programming) of the Spartan. The point being that only pure gate technologies will be used here because I do not understand so much more and have simplified (in my world) to use the Spartan as little as possible while keeping the overall size to a minimum.

All signals into the Spartan will have a 100Ohm series resistor from 5V external systems while the Spartan is not 5V tolerant. Ts_Enable can however be realized using 3,3V (HC-MOS can work down to 2V). The 40MHz crystal is intended to be a 5V DIL crystal which needs a 100Ohm resistor, this is also valid for the outputs of the 5V Tsw PROM (IC3) and the rotational encoder counters (IC6-7, HC191), the rotational encoder counters can however use 3,3V along with the Schmitt triggers (IC8).

While the trigger pulse for Ts_Enable comes from an "analog" 5V system I think it is more attractive to inject a 100Ohm resistor in series before Spartan.

In total I have to add 10pcs of 100Ohm resistors (I have checked that 3,3V is enough for high level on 5V systems).

New Version
This version will have a counter output for the auto trig function (10Tsw). It will also be incorporated with all the resistors needed for the Spartan interface.

I kind of think that 100 Ohms from 5V systems is a bit too low a resistance because let's say that there are input protection diodes at Spartan, the maximum input voltage is then 4V (3,3V+0,7V). (5V-4V)/100 is then 10mA. The Spartan itself can probably withstand this current but the units supplying this current will have to be able to supply 10mA. And I am right now not so certain that they can. The PROMs can but what about the DIL Crystal and the Sync Generator IC? I have checked that the recommended minimum supply voltage for the Sync Generator IC is 4V.

I have come to the conclusion that the sync-generation IC has open drain outputs which means that I can set the output to whatever I like (as long as it is lower than the 5V supply). So this IC does not need a series input resistor to the Spartan.

I have upgraded this picture somewhat, my philosophy is now that all ICs outside of the Spartan will run at 5V. This voltage (Vcc) is however not noted, the supply voltage is only noted for the 3,3V (Vdd) case. The Spartan needs to accept 5V through a resistor but it's 3,3V "core" can drive 5V logic.

I have revised this drawing somewhat because I suddenly decided that the counters for the rotational encoder will reside in the Spartan. The counters are actually not so special it was just that I have had a hard time realizing it. The counters are just simple up/down counters using a U/D' input and a CLK input. These gotta be available in the Spartan library and if the are not I can actually manufacture them using ordinary gates.

KOV, Oscilloscope TV module
The Lines Enabled (LE) part will be generated from the Spartan (with the aid of internal counters) and is thus 3,3V, all other signals are external and of the amplitude 5V.

The gates will be supplied with 5V and I have checked that 3,3V is enough for high level.

Epilogue
I have designed this TV Scope with the use of discrete logic capsules. So the whole design may be built using capsules only. The only problem is that the quantity of capsules will be rather high. I thus aim at reducing the number of capsules with the use of a Spartan FPGA. I have done some preliminary calculations and this seems to mean that the number of capsules drops from some 50 to 10. Designing it discretely however means the use of HC193 (my tip) but this counter only works to a frequency of some 32MHz (typically according to datasheet) while we sometimes run 40MHz. So this counter may have to be revised. A final thing is that I strongly recommend that all the signals in the PC Read feature are buffered while this saves the Spartan and the read memory. HC541 might suit the purpose.