MIPS Assembly/Arithmetic Instructions

Register Arithmetic Instructions
This instruction adds the two operands together, and stores the result in the destination register. Negative numbers are handled automatically using two's complement notation, so different instructions do not need to be used for signed and unsigned numbers.

The sub instruction subtracts the second source operand from the first source operand, and stores the result in the destination operand. In pseudo-code, the operation performs the following:

rd := rs - rt

Both add and sub trap if overflow occurs. However, some programming systems, like C, ignore integer overflow, so to improve performance "unsigned" versions of the instructions don't trap on overflow.

Multiplication and Division
The multiply and divide operations are slightly different from other operations. Even if they are R-type operations, they only take 2 operands. The result is stored in a special 64-bit result register. We will talk about the result register after this section.

This operation multiplies the two operands together, and stores the result in rd. Multiplication operations must differentiate between signed and unsigned quantities, because the simplicity of Two's Complement Notation does not carry over to multiplication. The mult instruction multiplies and sign extends signed numbers.

The result of multiplying 2 32-bit numbers is a 64-bit result. We will discuss the 64-bit results below.

The multu instruction multiplies the two operands together, and stores the result in rd. This instruction is for unsigned numbers only, and does not sign extend a negative result. This operation also creates a 64-bit result.

The div instruction divides the first argument by the second argument. The quotient is stored in the lowest 32-bits of the result register. The remainder is stored in the highest 32-bits of the result register. Like multiplication, division requires a differentiation between signed and unsigned numbers. This operation uses signed numbers.

Like the div instruction, this operation divides the first operand by the second operand. The quotient is stored in the lowest 32-bits of the result, and the remainder is stored in the highest 32-bits of the result. This operand divides unsigned numbers, and will not sign-extend the result.

64-Bit Results
The 64-bit result register is broken into two 32-bit segments: HI and LO. We can interface with these registers using the mfhi and mflo operations, respectively.

Takes only 1 operand. This instruction moves the high-32 bits of the result register into the target register.

Also takes only 1 operand. Moves the value from the LO part of the result register into the specified register.

If the upper (most significant) 32 bits of a product are unimportant to computation, programmers may save a step by using instructions that discard the upper 32 bits.

There is no unsigned version of the mul instruction. The mul instruction may also clobber the existing values in HI and LO.

Register Logic Instructions
These operations perform bit-wise logical operations on their operands.

Performs a bitwise AND operation on the two operands, and stores the result in rd.

Performs a bitwise OR operation on the two operands, and stores the result in rd.

Performs a bitwise NOR operation on the two operands, and stores the result in rd.

Performs a bitwise XOR operation on the two operands, and stores the result in rd.

Immediate Arithmetic Instructions
These instructions sign-extend the 16-bit immediate value to 32-bits and performs the same operation as the instruction without the trailing "i".

To subtract, use a negative immediate.

Immediate Logic Instructions
All logical functions zero-extend the immediate.

Takes the bitwise AND of rs with the immediate and stores the result in rt.

Takes the bitwise OR of rs with the immediate and stores the result in rt.

Takes the bitwise XOR of rs with a the immediate and stores the result in rt.

Shift instructions
Logical shift left: rd ← rt << shamt. Fills bits from right with zeros.

Logical shift right: rd ← rt >> shamt. Fills bits from left with zeros.

Arithmetic shift right. If rt is negative, the leading bits are filled in with ones instead of zeros: rd ← rt >> shamt.

Because not all shift amounts are known in advance, MIPS defines versions of these instructions that shift by the amount in the rs register. The behavior is otherwise identical.