Electronics/Basic gates

Basic Gates
There are 5 basic gates used in performing logic operations in Digital Electronic namely BUFFER gate, NOT gate, AND gate, OR gate, XOR gate. Each Logic Gate has A Symbol for easy to identify, a Mathematical Expression to identify mathematic logic operation and a Truth Table to completely describe operation of the Logic Gate

Five Basic Logic Gates

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! Digital gates !! Symbol!! Logic Operation !! Mathematic Expression
 * BUFFER|| [[Image:Buffer ANSI Labelled.svg|100px|Cổng Tiếp (Buffer Gate)]] || Y = BUFFER A || Y = A
 * NOT || [[Image:NOT_ANSI_Labelled.svg|100px]] || Y = NOT A || Y = $$\bar {A}$$
 * AND || [[Image:AND_ANSI_Labelled.svg|100px]] || Y = A AND B || Y = A . B
 * OR || [[Image:Logic-gate-or-us.png|100px]] || Y = A OR B || Y = A + B
 * XOR || [[Image:XOR_ANSI_Labelled.svg|100px]] || Y = A XOR B || Y = $${A \oplus B}$$
 * }
 * OR || [[Image:Logic-gate-or-us.png|100px]] || Y = A OR B || Y = A + B
 * XOR || [[Image:XOR_ANSI_Labelled.svg|100px]] || Y = A XOR B || Y = $${A \oplus B}$$
 * }
 * XOR || [[Image:XOR_ANSI_Labelled.svg|100px]] || Y = A XOR B || Y = $${A \oplus B}$$
 * }
 * }

The Truth Table of the five basic logic gates above
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! A !! B !! Q = A !! Q = NOT A !! Q = A AND B !! Q = A OR B !! Q = A XOR B
 * 0 || 0 || 0 ||1 || 0 || 0 || 0
 * 0 || 1 || 0 || 1 || 0 ||1 || 1
 * 1 || 0 || 1 || 0 || 0 ||1 || 1
 * 1 || 1 || 1 || 0 || 1 ||1 || 0
 * }
 * 1 || 0 || 1 || 0 || 0 ||1 || 1
 * 1 || 1 || 1 || 0 || 1 ||1 || 0
 * }
 * }
 * }

Complement of Basic Logic gates

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!Basic Gates !! Combination Gates!! Symbol !! Mathematical Expression
 * BUFFER|| Logic-gate-inv-us.png [[Image:Logic-gate-inv-us.png|100px|Cổng NOT (NOT Gate)]] || Buffer_ANSI_Labelled.svg || Q = is NOT NOT A Y = A
 * BUFFER|| Logic-gate-inv-us.png [[Image:Logic-gate-inv-us.png|100px|Cổng NOT (NOT Gate)]] || Buffer_ANSI_Labelled.svg || Q = is NOT NOT A Y = A


 * NOT || Buffer_ANSI_Labelled.svg [[Image:Logic-gate-inv-us.png|100px|Cổng NOT (NOT Gate)]] || [[Image:Logic-gate-inv-us.png|100px|Cổng NOT (NOT Gate)]] || Y = is NOT A


 * NAND || Logic-gate-and-us.png [[Image:Logic-gate-inv-us.png|100px|Cổng NOT (NOT Gate)]] || NAND_ANSI_Labelled.svg || Q = NOT A AND B


 * NOR || Logic-gate-or-us.png [[Image:Logic-gate-inv-us.png|100px|Cổng NOT (NOT Gate)]] || Logic-gate-nor-us.png || Y = NOT A OR B


 * XNOR || XOR_ANSI_Labelled.svg Logic-gate-inv-us.png || XNOR_ANSI_Labelled.svg || Q = NOT A XOR B
 * }
 * }

The Truth table of the combination gates above


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! A !! B !! Q = A !! Q = NOT A !! Q = A NAND B !! Q = A NOR B !! Q = A XNOR B
 * 0 || 0 || 0 ||1 || 1 || 1 || 1
 * 0 || 1 || 0 || 1 || 1 || 0 || 0
 * 1 || 0 || 1 || 0 || 1 || 0 || 0
 * 1 || 1 || 1 || 0 || 0 || 0 || 1
 * }
 * 1 || 0 || 1 || 0 || 1 || 0 || 0
 * 1 || 1 || 1 || 0 || 0 || 0 || 1
 * }
 * }
 * }

Summary

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!rowspan=2|Gates !rowspan=2|Function !colspan=2|Symbol !ANSI!!IEC !Buffer !NOT gate (Inverter) !AND gate !NAND gate (NOT−AND) !OR gate !NOR gate (NOT−OR) !XOR gate (Exclusive-OR) !XNOR gate (NOT−exclusive−OR)
 * $$Q=A$$
 * [[File:Buffer ANSI Labelled.svg]]
 * [[File:Buffer IEC Labelled.svg]]
 * $$Q=\overline{A}$$
 * [[File:NOT ANSI Labelled.svg]]
 * [[File:NOT IEC Labelled.svg]]
 * $$Q = A \cdot B$$
 * [[File:AND ANSI Labelled.svg]]
 * [[File:AND IEC Labelled.svg]]
 * $$Q = \overline{A \cdot B}$$
 * [[File:NAND ANSI Labelled.svg]]
 * [[File:NAND IEC Labelled.svg]]
 * $$Q = A + B$$
 * [[File:OR ANSI Labelled.svg]]
 * [[File:OR IEC Labelled.svg]]
 * $$Q = \overline{A + B}$$
 * [[File:NOR ANSI Labelled.svg]]
 * [[File:NOR IEC Labelled.svg]]
 * $$Q = A \oplus B$$
 * [[File:XOR ANSI Labelled.svg]]
 * [[File:XOR IEC Labelled.svg]]
 * $$Q = \overline{A \oplus B}$$
 * [[File:XNOR ANSI Labelled.svg]]
 * [[File:XNOR IEC Labelled.svg]]
 * }


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! width=3%| A !! width=3% | B !! width= 9% | Q = A !! width= 9% | Q = NOT A !! width= 9% | Q = A AND B !! width= 9% | Q = A OR B !! width= 9% | Q = A XOR B !! width= 9% | Q = A NAND B !! width= 9% | Q = A NOR B !! width= 9% | Q = A XNOR B
 * 0 || 0 || 0 ||1 || 0 || 0 || 0 || 1 ||1 || 1
 * 0 || 1 || 0 || 1 || 0 ||1 || 1 || 1 ||0 || 0
 * 1 || 0 || 1 || 0 || 0 ||1 || 1 || 1 ||0 || 0
 * 1 || 1 || 1 || 0 || 1 ||1 || 0 || 0 ||0 || 1
 * }
 * 1 || 0 || 1 || 0 || 0 ||1 || 1 || 1 ||0 || 0
 * 1 || 1 || 1 || 0 || 1 ||1 || 0 || 0 ||0 || 1
 * }
 * }
 * }