Digital Electronics/Logic Gates Summary

The table below summarize all the Basic Digital Gates and their characteristics


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!Basic Logic Gates  !! Symbol !! Mathmatical Formula !! Truth Table !! Constructions
 * Buffer || Buffer_ANSI_Labelled.svg || Q = A || A Q 0 0 1 1 ||
 * NOT || [[Image:NOT_ANSI_Labelled.svg|100px]] || Q = NOT A || A Q 0 1 1 0 ||
 * AND || [[Image:AND_ANSI_Labelled.svg|100px|Left|AND Gate]] || Q = A . B || A B Q 0 0 0 0 1 0 1 0 0 1 1 1 ||
 * NAND || NAND ANSI Labelled.svg|| Q =NOT (A . B) || A B Q 0 0 1 0 1 1 1 0 1 1 1 0 ||
 * OR || [[Image:Logic-gate-or-us.png|100px]] || Q = A + B || A B Q 0 0 0 0 1 1 1 0 1 1 1 1 ||
 * NOR || Logic-gate-nor-us.png|| Q = NOT (A + B) || A B Q 0 0 1 0 1 0 1 0 0 1 1 0 ||
 * XOR || [[Image:XOR ANSI Labelled.svg|100px]] || Q = A + B || A B Q 0 0 0 0 1 1 1 0 1 1 1 0 ||
 * XNOR || [[Image:XNOR ANSI Labelled.svg|100px]] || Q = A + B || A B Q 0 0 0 0 1 1 1 0 1 1 1 1 ||
 * }
 * OR || [[Image:Logic-gate-or-us.png|100px]] || Q = A + B || A B Q 0 0 0 0 1 1 1 0 1 1 1 1 ||
 * NOR || Logic-gate-nor-us.png|| Q = NOT (A + B) || A B Q 0 0 1 0 1 0 1 0 0 1 1 0 ||
 * XOR || [[Image:XOR ANSI Labelled.svg|100px]] || Q = A + B || A B Q 0 0 0 0 1 1 1 0 1 1 1 0 ||
 * XNOR || [[Image:XNOR ANSI Labelled.svg|100px]] || Q = A + B || A B Q 0 0 0 0 1 1 1 0 1 1 1 1 ||
 * }
 * XNOR || [[Image:XNOR ANSI Labelled.svg|100px]] || Q = A + B || A B Q 0 0 0 0 1 1 1 0 1 1 1 1 ||
 * }
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