Digital Electronics/Logic Gates/Combinational Gates

Combination gates
More than one logic gates can be connected to produce new logic gates

Buffer

 * {| class="wikitable" width=100%

!Basic Logic Gates !! Combinational Gates !! Symbol !! Mathmatical Formula !! Truth Table
 * Buffer || Logic-gate-inv-us.png [[Image:Logic-gate-inv-us.png|100px|Cổng NOT (NOT Gate)]] || Buffer_ANSI_Labelled.svg || Y = is NOT NOT A Y = A || A Q 0 0 1 1
 * }
 * }
 * }

NOT Gate

 * {| class="wikitable" width=100%

! Digital Gate !! Combinational Gates !! Symbol !! Mathematical Expression !! Truth Table
 * NOT Gate || Buffer_ANSI_Labelled.svg Logic-gate-inv-us.png || Logic-gate-inv-us.png || Y = is NOT A || A Y 0 1 1 0
 * }
 * }

NAND Gate

 * {| class="wikitable" width=100%

!Digital Gate !! Combinational Gate !! Symbol !! Mathematical Expression !! Truth Table
 * Buffer || Logic-gate-and-us.png Logic-gate-inv-us.png || Logic-gate-nand-us.png || Y = is NOT A.B  || A B Y 0 0 1 0 1 1 1 0 1 1 1 0
 * }
 * }

NOR Gate

 * {| class="wikitable" width=100%

!Digital Gate !! Combinational Gate !! Symbol !! Mathematical Expression !! Truth Table
 * NOT || Logic-gate-or-us.png [[Image:Logic-gate-inv-us.png|100px|Cổng NOT (NOT Gate)]] || Logic-gate-nor-us.png || Y = is NOT A+B  || A B Y 0 0 1 0 1 0 1 0 0 1 1 0
 * }
 * }

XNOR Gate

 * {| class="wikitable" width=100%

!Basic Gates !! Combinational Gate !! Symbol !! Mathematical Formula !! Truth Table
 * NOT Gate|| XOR_ANSI_Labelled.svg [[Image:Logic-gate-inv-us.png|100px]] || [[Image:XNOR_ANSI_Labelled.svg|100px]] || Y = is NOT AxorB  || A B Q 0 0 1 0 1 0 1 0 0 1 1 1
 * }
 * }


 * XNOR_Aufbau.png XNOR_using_NOR.svg