Clock and Data Recovery/Burst and Continuous transmission modes

It all depends on the target application

 * The function of the CDR is a simple one, but a few points must be clear to identify the best architecure.

From the CDR point of view
The first distinction to make is between the transient phase of acquisition of the correct phase lock and the steady-state phase of tracking.

During the acquisition phase the fundamental performance is the speed with which the lock-in is reached.

During the tracking phase instead, the performance that always matters is the jitter tolerance.


 * Only in case the CDR belongs to a regenerator, then two other performances also matter:


 * 1) the rejection of the incoming phase noise (measured by the jitter transfer function) and
 * 2) the minimization of the internally generated noise (measured by the characteristic of jitter generation).

From the application point of view
It is also necessary, in order to get a better understanding, to separate the burst-mode applications (those where the acquisition phase repeats itself regularly and therefore needs an efficient execution) from the continuous-mode applications (those where the acquisition phase takes place only exceptionally and where the performances to optimize are those related to the tracking phase).

It has been mentioned that different CDR architectures better fit different applications because they optimize the different performances required. In a single CDR, the attempt to improve all the performances at the same time creates conflicting requirements. Sometimes the solution is found by implementing more than a CDR in a cascade configuration. Some other times -more often- the best compromise is based on using the CDR structure that best fits the application.

It is even possible, thanks to modern DSP implementation of the loop filter, to change architecture according to the different operation phases. During acquisition, the first order would be used. Once acquisition is achieved, the filter parameters could be changed, so that the loop changes into a second order loop with more margin against bit errors and better jitter filtering (2.1) or less propagation to the output phase of the internal noise and zero steady state error (2.2).

This last approach however should be prudently taken by the designer, because the criteria to switch between architectures and the actual ways to implement the transition are tricky subjects with room for mistakes.

In conclusion, the best matching of applications and architectures is:

Each of the three fundamental architectures architecture will be studied separately, and its practical applications will be described:
 * For each architecture a first page develops the linear model, to have a good understanding of the relative merits of each choice and to have a good solid reference.
 * As the table above indicates, not always an implementation with linear phase comparator and linear VCO (that is well described by the mathematical model) is the best choice.


 * For each architecture again, a second page deals with the requirements of the applications and the choices that may make that architecture be preferred.
 * As anticipated in the table above, as often as not a bang-bang implementation gives the best fit.

Continuous transmission mode

 * where the slave CDR of the second order is preferred

A good part of the transmission links are of the continuous-mode type, where the signal is present at all times.

For this type of links it is not very important that the clock recovery circuit at the receiving end be fast in the initial phase of acquisition of the timing of the received signal.

The acquisition phase can last for a relatively long period, and the only thing that really matters is that a satisfactory locking of the phase of the received timing is reached within a reasonable time after the appearance of the received signal.

Examples of such links are: These links serve several users at the same time and shall be active all the time. Typical important cases can be: The clock recovery circuits, in the equipment described above (the ones represented in blue in the Figure above), must essentially provide good performances after the phase lock has been reached (after acquisition has been achieved). Performances during the lock-in (= acquisition) phase, that is when the connection is being established, are less important and can be traded off to some extent, in order to optimize the performances during normal transmission (that are the jitter transfer, generation and tolerance). The only thing that is really needed is the certainty that the phase lock will be achieved within a specified (not unreasonably long) time after the received signal has appeared.
 * High bit rate links inside the core of the networks. These are point-to-point (and bidirectional in all practical cases) links. The data flows, originated by different users (i.e. from different application processes in the OSIRM sense) are multiplexed on the link. The link shall be available at any time, given the importance of the traffic and in particular the need to support all QoS (Quality of Service, which primarily means no added time latency to the signals being carried by the link);
 * Point-to-multipoint links in the access networks (downstream direction).
 * Radio links from the base station to mobile phones (the continuous-mode clock recovery circuit to consider is the one at receiving end, inside the receiver part of the mobile phone);
 * Downstream transmission in LANs (Local Area Networks);
 * Downstream transmission of a PON (Passive Optical Network).

The ITU-T Recommendations (the G.7XX series and the G.8XX series in particular, see for instance the G.825) describe a lot of the characteristics of clock regeneration recommended for applications in continuous mode. With a little reverse engineering of the large amount of data available from that source (and making reference to the model of a PLL of the 2nd order, type 1), the preferred values that can be obtained are: ωn = 1/2500 ω0 ζ ≥ 0.66 (to match the requirement of 0.1 dB of max Jitter amplification).

ζ shall be at least larger than 0.66 in order to keep the maximum jitter amplification (maximum value of the jitter transfer function) below 0.1 dB. This is especially important in applications where several CDRs find themselves in a cascade of regenerators along a transmission link. Jitter at that particular frequency could be repeatedly amplified and accumulate along the line.

Another aspect that suggests values of ζ a bit larger than the classic 0.7 found in some early literature about PLL design, is the overshoot when tracking a sinusoidal jitter. Both the diagram of the jitter tolerance and the diagram of the jitter error show that (for ωn2 just above 1) there is an extra deterioration of the tracking performances for low values of ζ. Finally the construction tolerances when actually building the physical CDR circuit are to be considered. They can affect the design parameters significantly (sometimes as much as +/- 30%, like in the case of monolithic integrated circuits). In practice CDR for continuous mode applications will typically be designed with: ωn = 1/50 to 1/10,000 (typ. 1/1000) of ω0 ζ = 1.0 to 1.3 (typ. 1.1). An extreme case with ωn << ω0 can be found in long distance links on coaxial cable, where a high number of regenerators are located in series along the line, each one with its own CDR.

In that case the jitter accumulation is the performances to care about. The jitter transfer characteristic (that represents how the incoming jitter is filtered by the CDR) of each regenerator in the chain will have a very small bandwidth, with ωn/ω0 = 1/10000, while ζ stays higher than 0.652 to limit the jitter amplification at any frequency to be less than +0.1 dB in the worst case.

Another ITU reference goes even further and recommends that any peaking of the transfer function gain is to be avoided in long regenerator chains, which is the same as to recommend ζ never to be smaller than 0.7.

Burst transmission mode

 * where the first order phase aligner is often preferred

Applications of CDRs where the transmission is deliberately started and stopped (burst), with longer periods on inactivity in between bursts, are not less frequent than continuous mode applications. These burst-mode links are re-activated whenever significant data are to be transmitted, and stay inactive at any other time, to save energy from the transmitter supply and/or to leave time for other users to use the link. Examples can be:
 * Unidirectional links (remote controls for TV sets, for other appliances or industrial equipment, or for car keys) where batteries must be spared;
 * Upstream segments in multipoint access networks (where access time is to be shared with the other users, and where often also the energy taken from the transmitter battery or power supply must be used sparingly), like:
 * Radio links from mobile phones to the base station (the burst-mode clock recovery circuit to consider is the one at receiving end, inside the receiver part of the base station);
 * Upstream segment in a LAN (Local Area Network);
 * Upstream segment of a PON (Passive Optical Network).
 * All point-to-point bidirectional links (like walkie-talkies) where batteries must be spared.

In these cases of burst-mode clock recovery, the lock-in phase must be as short as possible as it represents a significant –useless- part of the time and energy spent for the connection. Performances in steady-state remain important, but performances during acquisition of the link become at least as important.

There are two different cases to distinguish, because the clock recovery requirements are different:
 * end point slave	The receiver has neither influence nor knowledge on the exact frequency of the transmitted signal. This is the case of many point-to-point burst-mode links, and a typical example can be the TV set that receives from a hand-held remote control. The receiver includes the CDR function in the most straightforward way possible.
 * phase aligner 	The receiver knows that the signal received is synchronous with a clock timing that is available also inside (often: that has been supplied by the same physical piece of equipment as) the receiver itself. Such is the case, for instance, in the upstream segment of radio cells of mobile phone networks, or in LANs, or in PONs, where the clock used for the upstream burst-mode transmissions is the same that has been sent to the periphery with the continuous-mode downstream signal. When the frequency is well known to the receiver, what is left to phase lock is simply a phase-aligner function.

Very often, to render the acquisition of phase lock easier, all bursts begin with a preamble of pulses that generate the maximum possible number of transitions.

The position of the transmitter and the receiver (or of the node and the terminal in a multipoint network) influence the transmission delay (or the turn-around delay in the multipoint network) of the timing signal.

The delay is measurable as an integer multiple of the cycle of the transmission clock, plus a fractional amount (at 1 GHz in open space one clock cycle corresponds to 30 cm, in a guided medium to a little less).

If the fractional amount happens to be very close to +/- on half clock cycle (i.e. tom +/- π), then the direction of the phase recovery at the beginning of the acquisition is uncertain. The acquisition may either go towards adding + π or in the opposite direction towards deducing π rad.

If the intersymbol interference affects the received signal, it is possible that initially (once or even a few times) the recovery of the corrects phase stutters back and forth, thereby prolonging the acquisition time.

When the acquisition has to take place frequently it must be reached in a short, well specified, time.

To avoid the risk of exceeding this time, the initial bits of the burst (= preamble bits, that come before the "payload" bits originated by the higher layers of the OSI stack) are fixed to:
 * 1) offer the maximum transition density
 * 2) not generate jitter from intersymbol interference.

In the common NRZ line coding for instance, the preamble bits for lock-in are:
 * 1 0 1 0 1 0 1 0 . ..

and shall last for as long as needed to get reasonably close to a good phase lock.

During this preamble, no meaningful data are transmitted, but the receiver can adjust to the (unknown) level of the received signal and to reach phase lock.

Burst preambles meant for phase lock vary, depending on the application, from as few as 6 to as many as 100 bit time intervals.