A-level Computing/AQA/Computer Components, The Stored Program Concept and the Internet/Machine Level Architecture/The Fetch–Execute cycle and the role of registers within it

The Fetch-Decode-Execute cycle of a computer is the process by which a computer: This cycle is repeated continuously by the central processing unit (CPU), from bootup to when the computer is shut down. In modern computers this means completing the cycle billions of times a second! Without it nothing would be able to be calculated.
 * 1) fetches a program instruction from its memory,
 * 2) determines what the instruction wants to do,
 * 3) and carries out those actions.

Registers/circuits involved
The circuits used in the CPU during the cycle are:
 * Program Counter (PC) - an incrementing counter that keeps track of the memory address of which instruction is to be executed next...
 * Memory Address Register (MAR) - the address in main memory that is currently being read or written
 * Memory Buffer Register (MBR) or Memory Data Register (MDR) - a register that holds data fetched from memory (and ready for the CPU to process) or data waiting to be stored in memory. This register can send or receive data via the Data Bus (2-way register).
 * Current Instruction register (CIR) - a temporary holding ground for the instruction that has just been fetched from memory
 * Control Unit (CU) - decodes the program instruction in the CIR, selecting machine resources such as a data source register and a particular arithmetic operation, and coordinates activation of those resources
 * Arithmetic logic unit (ALU) - performs mathematical and logical operations

Register notation
To describe the cycle we can use register notation. This is a very simple way of noting all the steps involved. In all cases where you see brackets e.g. [PC], this means that the contents of the thing inside the brackets is loaded. In the case of the first line, the contents of the program counter is loaded into the Memory Address Register.

$$MAR\gets [PC]$$

$$MBR\gets [Memory]_{MAR address}; PC\gets [PC]+1$$ (Increment the PC for next cycle at the same time)

$$CIR\gets [MBR]$$

$$[CIR]$$ decoded then executed

Detailed description of Fetch-Decode-Execute Cycle
To better understand what is going on at each stage we'll now look at a detailed description: The contents of the Program Counter, the address of the next instruction to be executed, is placed into the Memory Address Register

The address is sent from the MAR along the address bus to the Main Memory. The instruction at that address is found and returned along the data bus to the Memory Buffer Register. At the same time the contents of the Program Counter is increased by 1, to reference the next instruction to be executed.

The MBR loads the Current Instruction Register with the instruction to be executed.

The instruction is decoded and executed using the ALU if necessary.

The Cycle starts again!