360 Assembly/360 Instructions/BALR

Purpose of Instruction
BALR is a Branch and Link Register Instruction for use in transferring to different locations for code running in 24- 31, or 64-bit mode. It stores the address of the next sequential instruction in the target register, then jumps to the address specified in the source_register, unless register 0 is specified, in which case no branch is taken. This instruction remains for compatibility with 360 machines; for 370 and above, the BASR instruction is preferred.

Typical Usage
It is used in two cases. First, to establish a base register to address locations in the current module being executed. Second, it is used to call an external routine, saving the return address. Note that when registers are used in examples, the labels R0, R1, through R15 are used to represent the values 0 or 1 through 15, respectively.

Operation
The operation of this instruction is different depending on address mode.

24-bit operation
On 64-bit machines, the target register is loaded as follows: bits 0 to 31 are unchanged; bits 32-39 contain the instruction length code, condition cods, and program mask bits from the current PSW; bits 33 to 63 are loaded with the address of the next instruction following this one. If the source register is not 0, bits 33-63 of the source register are loaded into the PSW as the new next instruction address.

On 24- or 31-bit machines, or when operating in 24-bit mode, the target register is loaded as follows: bits 0 to 7 contain the instruction length code, condition cods, and program mask bits from the current PSW; bits 8 to 31 a loaded with the address of the next instruction following this one. If the source register is not 0, bits 8-31 of the source register are loaded into the PSW as the new next instruction address.

31-bit operation
On 64-bit machines, the target register is loaded as follows: bits 0 to 31 are unchanged; bit 32 is set to 1; bits 33 to 63 are loaded with the address of the next instruction following this one. If the source register is not 0, bits 33-63 of the source register are loaded into the PSW as the new next instruction address.

On 31-bit machines, or when operating in 31-bit mode, the target register is loaded as follows: bit 0 is set to 1; bits 2 to 31 are loaded with the address of the next instruction following this one. If the source register is not 0, bits 2-31 of the source register are loaded into the PSW as the new next instruction address.

64-bit operation
The address of the next instruction is loaded into bits 0-64 of the target register.

Source Register is zero
For the First example, establishing a base register, the format is  BALR R5,R0  The value of the current PC (Program Counter) plus 2 (the size of this instruction) is loaded into the target register (R5 in this case). Execution continues at the next instruction and no branch occurs.

Source Register not zero
For the Second example, calling an external routine, the format is  BALR R5,R3 It will store the Next Sequential Address after the BALR instruction in R5 and jump to the address stored in R3. R3 will have to have been preloaded before issuing this instruction with the address of the external routine, either by
 * an LA or LAY instruction
 * in 24- or 32-bit mode, with an L instruction of an A constant if the external routine is local to this module, or a V constant containing an external symbol if the external routine is in a different module, or
 * in 64-bit mode with an LG instruction of an AD constant.

Conventional usage
While the BALR instruction can be used for any type of subroutine call, either internal or external, when used with a non-zero source_register it primarily is used to call an external routine. The standard convention on IBM, Unisys and Fujitsu Operating Systems has been to use Register 14 as the target register, with Register 15 pre-loasded with the address of the external routine to call. Also, (in 24- and 32-bit applications) Register 13 is used to contain a 72-word storage area provided by the calling routine to allow the called routine to save Registers 14 and 0 through 12.

Typically for internal subroutines (within the same module), the BAL instruction is preferred.

Exceptions and Faults
The BALR instruction has no faults, however